k4j55323qf-gc Samsung Semiconductor, Inc., k4j55323qf-gc Datasheet - Page 18

• Manufacturer Part Number: k4j55323qf-gc
• Description: 256mbit Gddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

K4J55323QF-GC
COMMANDS
tion of each command. Two additional Truth Tables appear following the operation section : these tables provide current
state/next state information.
TRUTH TABLE - COMMANDs
TRUTH TABLE - DM Operation
Note :
Below Truth table-COMMANDs provides a quick reference of available commands. This is followed by a verbal descrip-
DESELECT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH (Enter self refresh mode)
LOAD MODE REGISTER
DATA TERMINATOR DISABLE
Write Enable
Write Inhibit
10. Used to mask write data ; provided coincident with the corresponding data.
11. Except DATA Termination disable.
1. CKE is HIGH for all commands except SELF REFRESH.
2. BA0~BA1 select either the mode register or the extended mode register (BA0=0, BA1=0 select the mode register;
3. BA0~BA1 provide bank address and A0~A11 provide row address.
4. BA0~BA1 provide bank address; A0~A7 and A9 provide column address; A8 HIGH enables the auto precharge feature
5. A8 LOW : BA0~BA1 determine which bank is precharged.
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; ll inputs and I/Os are "Don’t Care" except for CKE.
8. DESELECT and NOP are functionally interchangeable.
9. Cannot be in powerdown or self-refresh state.
BA0=1, BA1=0 select extended mode register; other combinations of BA0~BA1 are reserved). A0~A11 provide the op-code
to be written to the selected mode register.
(nonpersistent) , and A8 LOW disables the auto precharge feature.
A8 HIGH : All banks are precharged and BA0~BA1 are "Don’t Care."
Name (Function)
Name (Function)
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CS
H
L
L
L
X
L
L
L
L
DM
H
L
RAS
H
H
H
H
X
L
L
L
L
CAS
X
H
H
H
L
L
L
L
L
256M GDDR3 SDRAM
Valid
DQS
X
WE
H
H
H
H
H
X
L
L
L
Rev 1.7 (Jan. 2005)
Bank/Row
Bank/Col
Bank/Col
Op-Code
ADDR
Code
X
X
X
X
NOTES
10
NOTES
8, 11
6, 7
8
3
4
4
5
2