k4j55323qf-gc Samsung Semiconductor, Inc., k4j55323qf-gc Datasheet - Page 47

• Manufacturer Part Number: k4j55323qf-gc
• Description: 256mbit Gddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

AC CHARACTERISTICS - I
Note : 1. The WRITE latency can be set from 1 to 6 clocks. When the WRITE latency is set to 1 or 2 or 3 clocks, the input buffers are turned on during the
K4J55323QF-GC
DQS out access time from CK
CK high-level width
CK low-level width
CK cycle time
WRITE Latency
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
Active termination setup time
Active termination hold time
DQS input high pulse width
DQS input low pulse widthl
Data strobe edge to Dout edge
DQS read preamble
DQS read postamble
Write command to first DQS latching transition
DQS write preamble
DQS write preamble setup time
DQS write postamble
Half strobe period
Data output hold time from DQS
Data-out high-impedance window from CK and /CK t
Data-out low-impedance window from CK and /CK t
Address and control input hold time
Address and control input setup time
Address and control input pulse width
2. A low to high transition on the WDQS line is not allowed in the half clock prior to the write preamble.
3. The last rising edge of WDQS after the write postamble must be riven high by the controller. WDQS can not be pulled high by
4. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific
buffers are turned on during the WRITE commands for lower power operation.
ACTIVE commands reducing the latency but added power. When the WRITE latency is set to 4 or 6 clocks, must be greater than 7ns, the input
the on-die termination alone.
voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ).
Parameter
CL=9
CL=8
CL=7
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
DQSCK
CH
CL
CK
WL
DH
DS
ATS
ATH
DQSH
DQSL
DQSQ
RPRE
RPST
DQSS
WPRE
WPRES
WPST
HP
QH
HZ
LZ
IH
IS
IPW
t
tCHmin
WL-0.2 WL+0.2 WL-0.2 WL+0.2 WL-0.2 WL+0.2 WL-0.2 WL+0.2
tCLmin
HP
-0.26
0.45
0.45
0.18
0.18
0.48
0.48
0.35
0.35
Min
-0.3
-0.3
1.4
0.4
0.4
0.4
0.4
1.0
10
10
or
-0.16
5
0
-
-
-
-14
- 47 -
+0.26
0.160
Max
0.55
0.55
0.52
0.52
3.3
0.6
0.6
0.6
0.6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
t
tCHmin
tCLmin
HP
-0.26
0.45
0.45
0.18
0.18
0.48
0.48
0.35
0.35
Min
-0.3
-0.3
1.4
0.4
0.4
0.4
0.4
1.0
10
10
or
-0.16
5
0
-
-
-
-15
+0.26
0.160
Max
0.55
0.55
0.52
0.52
3.3
0.6
0.6
0.6
0.6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
t
tCHmin
tCLmin
HP
-0.29
0.20
0.20
0.45
0.45
0.48
0.48
Min
-0.3
-0.3
1.6
0.4
0.4
0.4
0.4
0.4
0.4
1.1
10
10
or
-0.18
5
0
-
-
-
256M GDDR3 SDRAM
-16
+0.29
0.180
Max
0.55
0.55
0.52
0.52
3.3
0.6
0.6
0.6
0.6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
tCHmin
tCLmin
0.225
-0.35
0.45
0.45
0.25
0.25
0.48
0.48
Min
t
-0.3
-0.3
2.0
0.4
0.4
0.4
0.4
0.5
0.5
1.3
10
10
HP
Rev 1.7 (Jan. 2005)
or
4
0
-
-
-
-
-20
+0.35
0.225
Max
0.55
0.55
0.52
0.52
3.3
0.6
0.6
0.6
0.6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Unit
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
1
2
3
4
4