ia82527 Innovasic Semiconductor Inc., ia82527 Datasheet - Page 23

• Manufacturer Part Number: ia82527
• Description: Serial Communications Controller?can Protocol
• Manufacturer: Innovasic Semiconductor Inc.

IA82527
CAN Serial Communications Controller
Table 3. Pin/Signal Descriptions (Continued)
ste
tx0
tx1
V
V
V
V
wr_n
CC
CC
SS1
SS2
Signal
/2
wr_n/wrl_n/r-w_n
int_n/ V
a3/ad3/ste
Name
V
V
V
tx0
tx1
SS1
SS2
CC
CC
/2
Pin
PLCC
43
26
25
24
23
20
1
7
PQFP
37
20
19
39
18
17
14
1
IA211080504-02
Page 23 of 53
synchronization transmission enable. Input. Serial
interface Mode. The logic level at the ste pin enables
the transmission of the synchronization bytes through
the IA82527 miso pin while the master device
transmits the Address and Control Byte as follows:
The IA82527 sends the synchronization bytes after the
cs_n signal has been asserted
Transmit (tx), lines 0 and 1. Output (push-pull). Pins
tx0 and tx1 are the outputs from the IA82527 to the
CAN bus lines.
During a recessive bit, tx0 is high and tx1 is low.
During a dominant bit, tx0 is low and tx1 is high.
Power (V
device. It must be connected to a +5V DC power
source.
Reference Voltage, ISO Physical Layer (V
Output. The V
the ISO low-speed physical layer:
This pin only functions as V
the CPU Interface Register (02H) is 1.
Ground, Digital (V
ground (0V) for the IA82527. It must be connected to
a V
Ground, Analog (V
(0V) for the IA82527 analog comparator. It must be
connected to a V
write. Input. Active Low. Mode 0. When wr_n is
asserted (low), it signals a write cycle.
When a logic 0 is placed on the ste pin, the
synchronization bytes sent through the miso pin are
00H and 00H.
When a logic 1 is placed on the ste pin, the
synchronization bytes sent through the miso pin are
AAH and 55H.
2.38V DC (minimum) to 2.60V DC (maximum)
(V
SS
CC
board plane.
= +5.00V; I
CC
). This pin provides power for the IA82527
CC
/2 pin provides a reference voltage for
SS
SS1
SS2
OUT
board plane.
). This pin provides the digital
). This pin provides the ground
Description
≤ 75 μA)
CC
/2 when the MUX bit of
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March 12, 2009
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Data Sheet
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/2).