ia82527 Innovasic Semiconductor Inc., ia82527 Datasheet - Page 38

• Manufacturer Part Number: ia82527
• Description: Serial Communications Controller?can Protocol
• Manufacturer: Innovasic Semiconductor Inc.

IA82527
CAN Serial Communications Controller
Table 11. Mode 2: General Bus Timing
a
the falling edge of e for the write and the rising edge of
2
A ―Read Cycle without a Previous Write‖ is where a read cycle follows a write cycle and where
Symbol
1/t
1/t
1/t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AVSL
SLAX
ELDZ
EHDV
QVEL
ELQX
ELDV
EHEL
SHSL
RSEH
SLEH
CLSL
ELCH
COPD
CHCL
t
XTAL
SCLK
MCLK
MCLK
.
Oscillator Frequency
System Clock Frequency
Memory Clock Frequency
Address Valid to as Low
Address Hold after as Low
Data Float after e Low
e High to Data Valid for Registers 02H, 04H, 05H
e High to Data Valid (all Registers except for 02H, 04H,
05H) for Read Cycle without a Previous Write
e High to Data Valid (all Registers except for 02H, 04H,
05H) for Read Cycle with a Previous Write
Data Setup to e Low
Input Data Hold after e Low
e Low to Output Data Valid on Port 1/2
e High Time
as High Time
Setup Time of r-w_n to e High
as Low to e High
cs_n Low to as Low
e Low to cs_n High
clkout Period (CD
Register representing the clkout divisor)
clkout High Period (CD
CLKOUT Register representing the clkout divisor)
V
is the value loaded in the CLKOUT
V
Parameter
is the value loaded in the
IA211080504-02
Page 38 of 53
a
e
for the read are separated by at least
(CD
Minimum
t
OSC
8 MHz
4 MHz
2 MHz
7.5 ns
V
10 ns
30 ns
20 ns
45 ns
30 ns
30 ns
20 ns
20 ns
0 ns
0 ns
0 ns
t
+ 1) ½
mclk
–
–
– 10
(CD
V
http://www.Innovasic.com
+ 1)
March 12, 2009
2 t
1.5 t
3.5 t
(CD
Customer Support:
t
Maximum
mclk
OSC
t
16 MHz
10 MHz
OSC
Data Sheet
8 MHz
[phone]
V
45 ns
45 ns
mclk
mclk
ns
ns
+ 500 ns
+ 1) ½
–
–
–
–
–
–
–
–
–
– 15
+ 100
+ 100