ia82527 Innovasic Semiconductor Inc., ia82527 Datasheet - Page 50

• Manufacturer Part Number: ia82527
• Description: Serial Communications Controller?can Protocol
• Manufacturer: Innovasic Semiconductor Inc.

IA82527
CAN Serial Communications Controller
Description:
the IE bit (Bit [1]) of the control register (0x00) is set, and any valid CAN bus message is seen
and acknowledged by the chip, a Msg Box 1 interrupt will be improperly generated.
Additionally, when the improper interrupt is generated, the IntPnd bit (Bits [1–0]) of Msg Box 1
Control_0 register (0x10) will not be set. This problem can occur even if the CAN bus message
is not stored by any message box or even if the MsgVal bit (Bits [7–6]) of Msg Box 1 Control_0
register (0x10) is reset. Normal behavior would be to not generate any receive interrupt on Msg
Box 1 unless the RXIE bit is set and a valid CAN message for Msg Box 1 is received.
Workaround:
register (0x10).
Errata No. 3
Problem: Message Box 15 receive interrupt enable does not work.
Description:
reset, and the IE bit (Bit [1]) of the control register (0x00) is set, Msg Box 15 receive interrupts
are generated when a message is received by Msg Box 15. The normal behavior for this
configuration would be for the RXIE bit to disable Msg Box 15 receive interrupts when
messages are received by Msg Box 15.
Workaround:
Errata No. 4
Problem: The CPU writes to Msg Box 15 RAM cannot be read back if MsgVal is set.
Description:
CPU writes to the Msg Box 15 arbitration 0–3 registers (0xF2–0xF5), and data 0–7 registers
(0xF7–0xFE) will operate properly, however CPU reads of these registers will return unknown
data. In other words, any CPU data written to Msg Box 15 will not be read back correctly if the
MsgVal bit is set. If the MsgVal bit (Bits [7–6]) of Msg Box 15 Control_0 register (0xF0) is
reset, CPU data written can be read back normally.
Workaround:
register (0xF0) before trying to read back any CPU data written to the Msg Box 15 arbitration
0–3 registers (0xF2–0xF5), and data 0–7 registers (0xF7–0xFE).
When the RXIE bit (Bits 3-2) of Msg Box 1 Control_0 register (0x10) is set, and
When the RXIE bit (Bits [3–2]) of the Msg Box 15 Control_0 register (0xF0) is
If the MsgVal bit (Bits [7–6]) of Msg Box 15 Control_0 register (0xF0) is set, any
The workaround is to not set RXIE bit (Bits [3–2]) of Msg Box 1 Control_0
There is no workaround.
The workaround is to clear the MsgVal bit (Bits [7–6]) of Msg Box 15 Control_0
IA211080504-02
Page 50 of 53
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March 12, 2009
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