dm9000a Davicom Semiconductor, Inc., dm9000a Datasheet - Page 10

• Manufacturer Part Number: dm9000a
• Description: Ethernet Controller With General Processor Interface
• Manufacturer: Davicom Semiconductor, Inc.

5. Pin Description
5.1 Processor Interface
5.1.1 8-bit mode pins
Final
Version: DM9000A-17-DS-F01
May 10, 2006
25,26,27
28,29,31
18,17,16,
14,13,12,
31,29,28,
27,26,25,
Pin No.
Pin No.
11,10
24,22
32
34
22
24
35
36
37
I = Input
# = asserted low
GP3,GP2,GP1
Pin Name
Pin Name
SD8~15
GP6~4
WAKE
SD0~7
LED3
IOW#
CMD
IOR#
CS#
INT
O = Output
I/O,PD
I/O,PD
O,PD
O,PD Issue a wake up signal when wake up event happens
O,PD
O,PD
Type
I,PD
Type
I,PD
I,PD
I,PD
I/O
Processor Read Command
This pin is low active at default, its polarity can be modified by EEPROM setting.
See the EEPROM content description for detail
Processor Write Command
This pin is low active at default, its polarity can be modified by EEPROM setting.
See the EEPROM content description for detail
Chip Select
A default low active signal used to select the DM9000A. Its polarity can be
modified by EEPROM setting. See the EEPROM content description for detail.
Command Type
When high, the access of this command cycle is DATA port
When low, the access of this command cycle is INDEX port
Interrupt Request
This pin is high active at default, its polarity can be modified by EEPROM
setting or by strap pin EECK. See the EEPROM content description for
detail
Processor Data Bus bit 0~7
Processor Data Bus bit 8~15
In 16-bit mode, these pins act as the processor data bus bit 8~15;
When EECS pin is pulled high , they have other definitions. See 8-bit mode pin
description for details.
Full-duplex LED
In LED mode 1, Its low output indicates that the internal PHY is operated
in full-duplex mode, or it is floating for the half-duplex mode of the internal
PHY
In LED mode 0, Its low output indicates that the internal PHY is operated
in 10M mode, or it is floating for the 100M mode of the internal PHY
Note: LED mode is defined in EEPROM setting.
General Purpose output pins:
These pins are output only for general purpose that are configured by
register 1Fh.
GP6 pin also act as trap pin for the INT output type.
When GP6 is pulled high, the INT is Open-Drain output type;
Otherwise it is force output type.
General I/O Ports
Registers GPCR and GPR can program these pins
I/O = Input/Output
PD = internal pull-low about 60K
Ethernet Controller with General Processor Interface
O/D = Open Drain
Description
Description
P = Power
DM9000A
10