dm9000a Davicom Semiconductor, Inc., dm9000a Datasheet - Page 38

• Manufacturer Part Number: dm9000a
• Description: Ethernet Controller With General Processor Interface
• Manufacturer: Davicom Semiconductor, Inc.

8.9 DAVICOM Specified Configuration and Status Register (DSCSR) - 17
Final
Version: DM9000A-17-DS-F01
May 10, 2006
17.15
17.14
17.13
17.12
17.11
-17.9
-17.4
16.0
17.8
Bit
Bit Name
PHYADR
Reserved
100HDX
100FDX
10HDX
10FDX
[4:0]
RLOUT
(PHYADR),
Default
1, RO
1, RO
1, RO
1, RO
0, RO
RW
0, RW
100M Full Duplex Operation Mode
After auto-negotiation is completed, results will be written to this
bit. If this bit is 1, it means the operation 1 mode is a 100M full
duplex mode. The software can read bit [15:12] to see which mode
is selected after auto-negotiation. This bit is invalid when it is not
in the auto-negotiation mode
100M Half Duplex Operation Mode
After auto-negotiation is completed, results will be written to this
bit. If this bit is 1, it means the operation 1 mode is a 100M half
duplex mode. The software can read bit [15:12] to see which mode
is selected after auto-negotiation. This bit is invalid when it is not
in the auto-negotiation mode
10M Full Duplex Operation Mode
After auto-negotiation is completed, results will be written to this
bit. If this bit is 1, it means the operation 1 mode is a 10M Full
Duplex mode. The software can read bit [15:12] to see which
mode is selected after auto-negotiation. This bit is invalid when it
is not in the auto-negotiation mode
10M Half Duplex Operation Mode
After auto-negotiation is completed, results will be written to this
bit. If this bit is 1, it means the operation 1 mode is a 10M half
duplex mode. The software can read bit [15:12] to see which mode
is selected after auto-negotiation. This bit is invalid when it is not
in the auto-negotiation mode
Reserved
Read as 0, ignore on write
PHY Address Bit 4:0
The first PHY address bit transmitted or received is the MSB of
the address (bit 4). A station management entity connected to
multiple PHY entities must know the appropriate address of each
PHY
mode and power down all circuit except oscillator and clock
generator circuit. When waking up from Sleep mode (write
this bit to 0), the configuration will go back to the state
before sleep; but the state machine will be reset
Remote Loopout Control
When this bit is set to 1, the received data will loop out to the
transmit channel. This is useful for bit error rate testing
Ethernet Controller with General Processor Interface
Description
DM9000A
38