dm9000a Davicom Semiconductor, Inc., dm9000a Datasheet - Page 30

• Manufacturer Part Number: dm9000a
• Description: Ethernet Controller With General Processor Interface
• Manufacturer: Davicom Semiconductor, Inc.

8.1 Basic Mode Control Register (BMCR) - 00
Final
Version: DM9000A-17-DS-F01
May 10, 2006
0.15
0.14
0.13
0.12
0.11
0.10
Bit
0.9
Speed selection
Auto-negotiatio
Auto-negotiation
Power down
Bit Name
Loopback
n enable
Restart
Isolate
Reset
0, RW/SC Reset
0,RW/SC Restart Auto-negotiation
Default
0, RW
1, RW
1, RW
0, RW
0,RW
1=Software reset
0=Normal operation
This bit sets the status and controls the PHY registers to their
default states. This bit, which is self-clearing, will keep
returning a value of one until the reset process is completed
Loopback
Loop-back control register
1 = Loop-back enabled
0 = Normal operation
When in 100Mbps operation mode, setting this bit may cause
the descrambler to lose synchronization and produce a 720ms
"dead time" before receive
Speed Select
1 = 100Mbps
0 = 10Mbps
Link speed may be selected either by this bit or by
auto-negotiation. When auto-negotiation is enabled and bit 12
is set, this bit will return auto-negotiation selected medium
type
Auto-negotiation Enable
1 = Auto-negotiation is enabled, bit 8 and 13 will be in
auto-negotiation status
Power Down
While in the power-down state, the PHY should respond to
management transactions.
1=Power down
0=Normal operation
Isolate
Force to 0 in application.
1 = Restart auto-negotiation. Re-initiates the auto-negotiation
process. When auto-negotiation is disabled (bit 12 of this
register cleared), this bit has no function and it should be
cleared. This bit is self-clearing and it will keep returning to a
value of 1 until auto-negotiation is initiated by the DM9000A.
The operation of the auto-negotiation process will not be
affected by the management entity that clears this bit
0 = Normal operation
Ethernet Controller with General Processor Interface
Description
DM9000A
30