dm9000a Davicom Semiconductor, Inc., dm9000a Datasheet - Page 50
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dm9000a
Manufacturer Part Number
dm9000a
Description
Ethernet Controller With General Processor Interface
Manufacturer
Davicom Semiconductor, Inc.
Datasheet
1.DM9000A.pdf
(60 pages)
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10.3.4 Processor I/O Write Timing
Note:(the default clk period is 20ns)
1. The IO16 is valid when the SD bus width is 16-bit
Final
Version: DM9000A-17-DS-F01
May 10, 2006
Symbol
T
and system address is DATA port (i.e. CMD is high)
and the value of INDEX port is memory data
2
T
T
T
T
T
T
T
T
T
+T
1
2
3
4
5
6
6
7
8
6
SD
IO16
CS#,CMD valid to IOW# valid
IOW# Width
System Data(SD) Setup Time
System Data(SD) Hold Time
IOW# Invalid to CS#,CMD Invalid
IOW# Invalid to next IOW#/IOR# valid
When write DM9000A INDEX port
IOW# Invalid to next IOW#/IOR# valid
When write DM9000A DATA port
IOW# Invalid to next IOW#/IOR# valid
When write DM9000A memory
CS#,CMD Valid to IO16 valid
CS#,CMD Invalid to IO16 Invalid
CS# , CMD
IOW#
→
→
Parameter
T1
←
←
T7
←
Ethernet Controller with General Processor Interface
←
T2
T3
register index (ex. F0H, F2H, F6H or F8H)
→
→
→
→
←
Min.
→
10
10
0
3
0
1
2
1
←
←
T6
←
T5
T4
∫∫
T8
→
Typ.
DM9000A
Max.
3
3
Unit
clk*
clk*
clk*
ns
ns
ns
ns
ns
ns
ns
50