dq8051 Digital Core Design, dq8051 Datasheet - Page 3

• Manufacturer Part Number: dq8051
• Manufacturer: Digital Core Design

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rate between HAD and Silicon
Hardware watch‐points activated at a certain
Automatic adjustment of debug data transfer speed
JTAG Communication interface
Power Management Unit
Power management mode
Switchback feature
Stop mode
Extended Interrupt Controller
2 priority levels
2 external interrupt sources
3 interrupt sources from peripherals
Four 8‐bit I/O Ports
Bit addressable data direction for each line
Read/write of single line and 8‐bit group
Two 16‐bit timer/counters
Timers clocked by internal source
Auto reload 8‐bit timers
Externally gated event counters
Full‐duplex serial port
Synchronous mode, fixed baud rate
8‐bit asynchronous mode, fixed baud rate
9‐bit asynchronous mode, fixed baud rate
9‐bit asynchronous mode, variable baud rate
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Special Function Registers (SFRs)
External Data Memory
address by any write into memory
address by any read from memory
address by write into memory a required data
address by read from memory a required data
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Copyright© 1999‐2011 DCD – Digital Core Design. All Rights Reserved
can be easy adjusted to requirements of dedicated
application and technology. Configuration of the
core can be prepared by effortless changing ap‐
propriate constants in package file. There is no
need to change any parts of the code.
Besides mentioned above parameters all available
peripherals and external interrupts can be ex‐
cluded from the core by changing appropriate
constants in package file.
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The following parameters of the DQ8051 core
Second Data Pointer (DPTR1)
DPTR0 decrement
DPTR1 decrement
Data Pointers auto‐switch
Data Pointers auto‐update
Interrupts
Power Management Mode
Stop mode
Peripherals
Synchronous XDM
DoCD™ debug unit
C O N F I G U R A T I O N
‐ used
‐ unused
‐ used
‐ unused
‐ used
‐ unused
‐ used
‐ unused
‐ used
‐ unused
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‐ used
‐ unused
‐ used
‐ unused
‐ used
‐ unused
‐
‐
‐ used
‐ unused
subroutines
location
size