dq8051 Digital Core Design, dq8051 Datasheet - Page 4

• Manufacturer Part Number: dq8051
• Manufacturer: Digital Core Design

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Comprehensible and clearly defined licensing
methods without royalty per chip fees make using
of IP Core easy and simply.
Single Site license option is dedicated for small and
middle sized companies making its business in one
place.
Multi Sites license option is dedicated for corpo‐
rate customers making its business in several
places. Licensed product can be used in selected
branches of corporate.
In all cases number of IP Core instantiations within
a project, and number of manufactured chips are
unlimited. The license is royalty per chip free.
There is no time of use restrictions.
There are two formats of delivered IP Core
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called HDL Source
Source code:
VHDL & VERILOG test bench environment
Technical documentation
Synthesis scripts
Example application
Technical support
VHDL, Verilog RTL synthesizable source code
FPGA EDIF/NGO/NGD/QXP/VQM called Netlist
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VHDL Source Code or/and
VERILOG Source Code or/and
FPGA netlist
Active‐HDL automatic simulation macros
ModelSim automatic simulation macros
Tests with reference responses
Installation notes
HDL core specification
Datasheet
IP Core implementation support
3 months maintenance
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Delivery the IP Core updates, minor and
major versions changes
Delivery the documentation updates
Phone & email support
D E L I V E R A B L E S
L I C E N S I N G
All trademarks mentioned in this document are trademarks of their respective owners.
Copyright© 1999‐2011 DCD – Digital Core Design. All Rights Reserved
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operation with Internal or External Program
Memory. Program Memory can be imple‐
mented as ROM, RAM or FLASH.
MB of External Data Memory. Extra DPX (Data
Pointer eXtended) register is used for segments
swapping.
kB of fast on‐chip Synchronous External Data
Memory. All reads and writes are executed in
one clock cycle.
PROGRAM
INTERNAL
Memory of up to 256 bytes The Internal Data
Memory can be implemented as synchronous
RAM.
EXTERNAL
SYNCHRONOUS
USER
tion Registers (ESFRs) may be added to the
DQ8051 design. ESFRs are memory
mapped into Direct Memory between ad‐
dresses 0x80 and 0xFF in the same manner
as core SFRs and may occupy any address
that is not occupied by a core SFR.
WAIT
operation with wide range of Program and
Data memories. Slow Program and Exter‐
nal Data memory may assert a memory
Wait signal to hold up CPU activity.
The DQ8051 soft core is dedicated for
The DQ8051 can address Internal Data
The DQ8051 soft core can address up to 16
The DQ8051 soft core can address up to 64
The DQ8051 soft core is dedicated for
Up to 60 External (user) Special Func‐
D E S I G N F E A T U R E S
SPECIAL
STATES
DATA
DATA
MEMORY:
SUPPORT:
FUNCTION
XDM:
MEMORY:
MEMORY:
REGISTERS: