dq8051 Digital Core Design, dq8051 Datasheet - Page 8

• Manufacturer Part Number: dq8051
• Manufacturer: Digital Core Design

scalable unit and some features can be turned off
to save silicon and reduce power consumption. A
special care on power consumption has been
taken, and when debugger is not used it is auto‐
matically switched in power save mode. Finally
whole debugger is turned off when debug option is
no longer used.
Timers – System timers’ module. Contains two 16
bits configurable timers: Timer 0 (TH0, TL0), Timer
1 (TH1, TL1) and Timers Mode (TMOD) registers. In
the timer mode, timer registers are incremented
every 12 CLK periods when appropriate timer is
enabled. In the counter mode the timer registers
are incremented every falling transition on their
corresponding input pins (T0, T1), if gates are
opened (GATE0, GATE1). T0, T1 input pins are
sampled every CLK period. It can be used as clock
source for UARTs.
UART0 – Universal Asynchronous Receiver &
Transmitter module is full duplex, meaning it can
transmit and receive concurrently. Includes Serial
Configuration register (SCON), serial receiver and
transmitter buffer (SBUF) registers. Its receiver is
double‐buffered, meaning it can commence recep‐
tion of a second byte before a previously received
byte has been read from the receive register. Writ‐
ing to SBUF0 loads the transmit register, and read‐
ing SBUF0 reads a physically separate receive reg‐
ister. It works in 3 asynchronous and 1 synchro‐
nous modes. UART0 can be synchronized by Timer
1 or Timer 2.
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