ch7004c Chrontel, ch7004c Datasheet - Page 37

• Manufacturer Part Number: ch7004c
• Description: Digital Pc To Tv Encoder With Macrovisiontm
• Manufacturer: Chrontel

CHRONTEL
Power Management Register
This register provides control of the power management functions, a software reset (Reset*) and the SCART output
enable. The CH7004 provides programmable control of its operating states, as described in the table below.
Reset* (bit 3) is soft reset. Setting this bit will reset all circuitry requiring a power on reset, except for this bit itself
and the serial port state machines.
SCART (bit 4) is the SCART enable. Setting SCART = 0 means the CH7004 will operate normally, outputting Y/C
and CVBS from the three DACs. SCART=1 enables SCART output, which will cause R, G and B to be output from
the DACs and composite sync from the CSYNC pin.
Note: For complete details regarding the operation of these modes, see the Power Management in Functional Description
sections.
Connection Detect Register
The Connection Detect Register provides a means to sense the connection of a TV to either S-Video or Composite
video outputs. The status bits, YT, CT, and CVBST correspond to the DAC outputs for S-Video (Y and C outputs)
and Composite video (CVBS), respectively. However, the values contained in these status bits are NOT VALID
until a sensing procedure is performed. Use of this register requires a sequence of events to enable the sensing of
outputs, then reading out the applicable status bits. The detection sequence works as follows:
1.
2.
3.
4.
201-0000-024 Rev. 2.4, 6/24/2004
Table 23. Power Management
Bit:
Symbol:
Type:
Default:
000
001
010
011
1XX
Bit:
Symbol:
Type:
Default:
Set the SENSE bit to a 1. This forces a constant current output onto the Y, C, and CVBS outputs. Note that during
Ensure the power management register Bits 2-0 are set to 011 (normal mode).
SENSE = 1, these 3 analog outputs are at steady state and no TV synchronization pulses are asserted.
Reset the SENSE bit to 0. This triggers a comparison between the voltage sensed on these analog outputs and the
reference value expected (V
connected, if it is above this voltage it is considered unconnected. During this step, each of the three status bits
corresponding to individual analog outputs will be set if they are NOT connected.
Read the status bits. The status bits, Y, C, and CVBST (corresponding to S-Video Y and C outputs and composite
video) now contain valid information which can be read to determine which outputs are connected to a TV. Again, a
“0” indicates a valid connection, a “1” indicates an unconnected output.
PD[2:0]
7
7
Composite Off
Power Down
S-Video Off
Normal (On)
Full Power Down
Operating State
6
6
threshold
= 1.235V). If the measured voltage is below this threshold value, it is considered
5
5
CVBS DAC is powered down
All circuits and pins are active.
Most pins and circuitry are disabled (except for the buffered clock outputs
which are limited to the 14MHz output and VCO divided outputs).
S-Video DACs are powered down
All circuitry is powered down, except serial port circuit
4
SCART
R/W
0
4
3
Reset*
R/W
1
3
YT
R
0
Functional Description
2
PD2
R/W
0
2
CT
R
0
Symbol: PMR
Address: 0EH
Bits: 5
Symbol: CDR
Address: 10H
Bits: 4
1
PD1
R/W
1
1
CVBST
R
0
CH7004C
0
PD0
R/W
1
0
SENSE
W
0
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