ch7004c Chrontel, ch7004c Datasheet - Page 39

• Manufacturer Part Number: ch7004c
• Description: Digital Pc To Tv Encoder With Macrovisiontm
• Manufacturer: Chrontel

CHRONTEL
PLL Overflow Register
The PLL Overflow Register contains the MSB bits for the ‘M’ and ‘N’ vlaues, which will be described in the PLL-
M and PLL-N registers, respectively. The reserved bits should not be written to.
PLL M Value Register
The PLL M value register determines the division factor applied to the frequency reference clock before it is input to
the PLL phase detector when the CH7004 is operating in master or pseudo-master clock mode. In slave mode, an
external pixel clock is used instead of the frequency reference, and the division factor is determined by the
XCM[3:0] value. This register contains the lower 8 bits of the complete 9-bit M value.
PLL N Value Register
The PLL N value register determines the division factor applied to the VCO output before being applied to the PLL phase
detector, when the CH7004 is operating in master or pseudo-master mode. In slave mode, the value of ‘N’ is always 1.
This register contains the lower 8 bits of the complete 10-bit N value. The pixel clock generated in a master and pseudo-
master modes is calculated according to the equation below:
When using a 14.318 MHz frequency reference, the required M and N values for each mode are shown in the table
below.
201-0000-024 Rev. 2.4, 6/24/2004
Bit:
Symbol:
Type:
Default:
Bit:
Symbol:
Type:
Default:
Bit:
Symbol:
Type:
Default:
7
7
M7
R/W
0
7
N7
R/W
1
Fpixel = Fref* [(N+2) / (M+2)]
6
6
M6
R/W
1
6
N6
R/W
0
5
5
M5
R/W
0
5
N5
R/W
0
4
Reserved
R/W
0
4
M4
R/W
0
4
N4
R/W
0
3
Reserved
R/W
0
3
M3
R/W
0
3
N3
R/W
0
2
N9
0
2
M2
0
2
N2
0
R/W
R/W
R/W
Symbol: MNE
Address: 13H
Bits: 5
Symbol: PLLM
Address: 14H
Bits: 8
Symbol: PLLN
Address: 15H
Bits: 8
1
N8
R/W
0
1
M1
R/W
0
1
N1
R/W
0
CH7004C
0
M8
R/W
0
0
M0
R/W
1
0
N0
R/W
0
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