ch7004c Chrontel, ch7004c Datasheet - Page 6

• Manufacturer Part Number: ch7004c
• Description: Digital Pc To Tv Encoder With Macrovisiontm
• Manufacturer: Chrontel

CHRONTEL
Pixel Data: Active pixel data will be expected after a programmable number pixels times the multiplex rate after the
leading edge of Horizontal Sync. In other words, specifying the horizontal back porch value (as a pixel count), plus
horizontal sync width, will determine when the chip will begin to sample pixels.
4.1 Non-multiplexed Mode
In the 15/16-bit mode shown in Figure 4, the pixel data bus represents a 15/16-bit non-multiplexed data stream,
which contains either RGB or YCrCb formatted data. When operating in RGB mode, each 15/16-bit Pn value will
contain a complete pixel encoded in either 5-6-5 or 5-5-5 format. When operating in YCrCb mode, each 16-bit Pn
word will contain an 8-bit Y (luminance) value on the upper 8 bits, and an 8-bit C (color difference) value on the
lower 8 bits. The color difference will be transmitted at half the data rate of the luminance data, with the
sequencebeing set as Cb followed by Cr. The Cb and Cr data will be co-sited with the Y value transmitted with the
Cb value, with the data sequence described in Table 3. The first active pixel is SAV pixels after the trailing edge of
horizontal sync, where SAV is a bus-controlled register.
When IDF = 1, (YCrCb 16-bit mode), H and V sync signals can be embedded into the data stream. In this mode, the
embedded sync will be similar to the CCIR656 convention (not identical, since that convention is for 8-bit data
streams), and the first byte of the ‘video timing reference code’ will be assumed to occur when a Cb sample would
occur – if the video stream was continuous. This is delineated in Table 4 below.
6
Table 3. 15/16-bit Non-multiplexed Data Formats
Pixel#
Bus Data
Format
IDF#
HSYNC
POut/
XCLK
Pixel
Data
D[15]
D[14]
D[13]
D[12]
D[11]
D[10]
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
t
HD
t
HSW
P0
R0[4]
R0[3]
R0[2]
R0[1]
R0[0]
G0[5]
G0[4]
G0[3]
G0[2]
G0[1]
G0[0]
B0[4]
B0[3]
B0[2]
B0[1]
B0[0]
RGB 5-6-5
Figure 4: Non-multiplexed Data Transfers
SAV
AVR
0
P1
R1[4]
R1[3]
R1[2]
R1[1]
R1[0]
G1[5]
G1[4]
G1[3]
G1[2]
G1[1]
G1[0]
B1[4]
B1[3]
B1[2]
B1[1]
B1[0]
P2
x
R2[4]
R2[3]
R2[2]
R2[1]
R2[0]
G2[4]
G2[3]
G2[2]
G2[1]
G2[0]
B2[4]
B2[3]
B2[2]
B2[1]
B2[0]
RGB 5-5-5
P0a
P0
3
P3
x
R3[4]
R3[3]
R3[2]
R3[1]
R3[0]
G3[4]
G3[3]
G3[2]
G3[1]
G3[0]
B3[4]
B3[3]
B3[2]
B3[1]
B3[0]
t
t
P 1
P
P0b
P1
t
t
P0
Y0[7]
Y0[6]
Y0[5]
Y0[4]
Y0[3]
Y0[2]
Y0[1]
Y0[0]
Cb0[7]
Cb0[6]
Cb0[5]
Cb0[4]
Cb0[3]
Cb0[2]
Cb0[1]
Cb0[0]
SP1
SP
P1a
P2
t
t
t
PH 1
PH
HP
t
HP1
201-0000-024 Rev. 2.4, 6/24/2004
P1b
P3
P1
Y1[6]
Y1[5]
Y1[4]
Y1[3]
Y1[2]
Y1[1]
Y1[0]
Cr0[4]
Cr0[3]
Cr0[2]
Cr0[1]
Cr0[0]
Y1[7]
Cr0[7]
Cr0[6]
Cr0[5]
YCrCb (16-bit)
P2a
P4
1
P2
Y2[7]
Y2[6]
Y2[5]
Y2[4]
Y2[3]
Y2[2]
Y2[1]
Y2[0]
Cb2[7]
Cb2[6]
Cb2[5]
Cb2[4]
Cb2[3]
Cb2[2]
Cb2[1]
Cb2[0]
CH7004C
P2b
P5
P3
Y3[7]
Y3[6]
Y3[5]
Y3[4]
Y3[3]
Y3[2]
Y3[1]
Y3[0]
Cr2[7]
Cr2[6]
Cr2[5]
Cr2[4]
Cr2[3]
Cr2[2]
Cr2[1]
Cr2[0]