ch7301c Chrontel, ch7301c Datasheet
ch7301c
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ch7301c Summary of contents
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... The DVI processor includes a low jitter PLL for generation of the high frequency serialized clock, and all circuitry required to encode, serialize and transmit data. CH7301C comes in versions able to drive a DFP display at a pixel rate 165MHz, supporting UXGA resolution displays. No scaling of input data is performed on the data output to the DVI device ...
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... DE 3 VREF DGND 7 GPIO[1] / HPINT 8 GPIO[0] 9 HPDET DGND 12 DVDD 13 RESET* 14 SPD 15 SPC 16 N/C 2 Chrontel CH7301C Figure 2. 64-Pin LQFP 201-0000-056 CH7301C 48 HSYNC 47 VSYNC DVDDV GND TEST 35 ISET 34 GND 33 VDD Rev. 1.32, 5/24/2005 ...
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... When this pin is low, the device is held in the power-on reset condition. When this pin is high, reset is controlled through the serial port register. Serial Port Data Input / Output This pin functions as the serial data pin of the serial port interface, and uses the DVDDV supply. CH7301C 3 ...
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... Blue Output This pin will output the Blue component of RGB when RGB bypass mode is used. No Connect Vertical Sync Output A buffered version of VGA vertical sync can be acquired from this pin. (Refer to Register 21h, DC register) 201-0000-056 CH7301C A 140 ohm resistor should be Rev. 1.32, 5/24/2005 ...
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... The levels are 0 to DVDDV, and the VREF signal is used as the threshold level. External Clock Inputs These inputs form a differential clock signal input to the CH7301C for use with the and D[11:0] data. If differential clocks are not available, the XCLK* input should be connected to VREF. ...
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... YCrCb or RGB in this operating mode (See description for register 56h, bit[0). Input data is 2X multiplexed, and the XCLK clock signal can times the pixel rate. The CH7301C can support a pixel rate of 165MHz. This operating mode uses all 10 bits of the DAC’s 10-bit range, and provides a nominal signal swing of 0.661V (or 0.7V depending on DAC Gain setting in control registers) when driving a 75 conversion or flicker filtering is applied in RGB bypass ...
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... DDR). For the multiplexed data, clock at 2X pixel rate, the data applied to the CH7301C is latched with one edge of the clock (also known as single edge transfer mode or SDR). The polarity of the pixel clock can be reversed under serial port control. In single edge transfer modes, the clock edge used to latch data is programmable ...
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... The 12 data inputs support 5 different multiplexed data formats, each of which can be used with a 1X clock latching data on both clock edges clock latching data with a single edge. The data received by the CH7301C can be used to drive the DVI output, the VGA to TV encoder, or directly drive the DAC’s. The multiplexed input data formats are ...
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... P[7:0] (Blue Data) Figure 4. Multiplexed Input Data Formats (IDF = 0, 1) 201-0000-056 Rev. 1.32, 5/24/2005 SAV P0a P0b P0b[3:0], P0a[11:8] P0b[11:7], P0b[3:1] P0b[6:4], P0a[11:9], P0b[0], P0a[3] P0a[8:4], P0a[2:0] CH7301C P1a P1b P2a P2b P0b[11:4] P1b[11:4] P2b[11:4] P2b[3:0], P1b[3:0], P1a[11:8] P2a[11:8] P0a[7:0] P1a[7:0] P2a[7:0] P2b[11:7] ...
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... The following data is latched for IDF = 4 CRA (internal signal) P[23:16] (Y Data) P[15:8] (CrCb Data) P[7:0] (ignored) Figure 5. Multiplexed Input Data Formats (IDF = SAV P0a P0b P0b[6:4], P0a[11:9] P0b[5:4], P0a[11:9] CH7301C P1a P1b P2a P2b P0b[11:7] P1b[11:7] P2b[11:7] P2b[6:4], P1b[6:4], P1a[11:9] P2a[11:9] P0a[8:4] P1a[8:4] P2a[8:4] P0b[10:6] P1b[10:6] ...
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... RGB 5-6-5 P0b P1a P1b P0a R0[7] G1[4] R1[7] G0[5] R0[6] G1[3] R1[6] G0[4] R0[5] G1[2] R1[5] G0[3] R0[4] B1[7] R1[4] B0[7] R0[3] B1[6] R1[3] B0[6] G0[7] B1[5] G1[7] B0[5] G0[6] B1[4] G1[6] B0[4] G0[5] B1[3] G1[5] B0[3] 4 YCrCb 8-bit P0b P1a P1b P2a Y0[7] Cr0[7] Y1[7] Cb2[7] Y0[6] Cr0[6] Y1[6] Cb2[6] Y0[5] Cr0[5] Y1[5] Cb2[5] Y0[4] Cr0[4] Y1[4] Cb2[4] Y0[3] Cr0[3] Y1[3] Cb2[3] Y0[2] Cr0[2] Y1[2] Cb2[2] Y0[1] Cr0[1] Y1[1] Cb2[1] Y0[0] Cr0[0] Y1[0] Cb2[0] CH7301C 1 12-bit RGB (12-12) P0b P1a P1b R0[7] G1[4] R1[7] R0[6] G1[3] R1[6] R0[5] G1[2] R1[5] R0[4] B1[7] R1[4] R0[3] B1[6] R1[3] G0[7] B1[5] G1[7] G0[6] B1[4] G1[6] G0[5] B1[3] G1[5] R0[2] G1[0] R1[2] R0[1] B1[2] R1[1] R0[0] B1[1] R1[0] G0[1] B1[0] G1[1] 3 RGB 5-5-5 P0b P1a P1b X G1[5] X R0[7] G1[4] R1[7] R0[6] G1[3] R1[6] R0[5] B1[7] R1[5] R0[4] B1[6] R1[4] R0[3] B1[5] R1[3] G0[7] B1[4] G1[7] G0[6] B1[3] G1[6] P2b P3a P3b Y2[7] ...
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... SAV (synchronization reference at the start of active video) Bits S[7] and S[3..0] are ignored YCrCb 8-bit P1a P1b P2a P2b 00 S[7] Cb2[7] Y2[7] 00 S[6] Cb2[6] Y2[6] 00 S[5] Cb2[5] Y2[5] 00 S[4] Cb2[4] Y2[4] 00 S[3] Cb2[3] Y2[3] 00 S[2] Cb2[2] Y2[2] 00 S[1] Cb2[1] Y2[1] 00 S[0] Cb2[0] Y2[0] 201-0000-056 CH7301C P3a P3b Cr2[7] Y3[7] Cr2[6] Y3[6] Cr2[5] Y3[5] Cr2[4] Y3[4] Cr2[3] Y3[3] Cr2[2] Y3[2] Cr2[1] Y3[1] Cr2[0] Y3[0] Rev. 1.32, 5/24/2005 ...
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... EGISTER ONTROL The CH7301C is controlled via a serial port. The serial port bus uses only the SPC clock to latch data into registers, and does not use any internally generated clocks so that the device can be written to in all power down modes. The device retains all register states ...
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... XCLK is twice the pixel frequency (single edge clocking mode). Bit 2 of register CM controls the phase of the XCLK clock input to the CH7301C. A value of ‘1’ inverts the XCLK signal at the input of the device. This control is used to select which edge of the XCLK signal to use for latching input data ...
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... XCLK behind Data STEP XCLK behind Data STEP XCLK behind Data STEP XCLK behind Data STEP XCLK behind Data STEP HPIR Reserved Reserved R/W R/W R CH7301C Symbol: IC Address: 1Dh XCMD0 R/W R Symbol: GPIO Address: 1Eh Reserved R/W R ...
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... CHRONTEL Bit 3 of register GPIO resets the hot plug detection circuitry. A value of ‘1’ causes the CH7301C to release the GPIO[1]/HPINT pin. When a hot plug interrupt is asserted by the CH7301C, the CH7301C driver should read the DVIT bit in register 20h to determine the state of the DVI termination. After having read this, the HPIR bit should be set high to reset the circuit, and then set low again. In order to reset the HPIR bit high, DVIP and DVIL bits of register 49h[7:6] must first be set to ’ ...
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... Bits 2-1 of register DC control the DAC gain. DACG1 should be low when the input data format is RGB (IDF = 0- 3), and high when the input data format is YCrCb (IDF = 4). Bits 3 of register DC enables the HSYNC and VSYNC outputs. 201-0000-056 Rev. 1.32, 5/24/2005 R/W R/W R CH7301C Symbol: DC Address: 21h DACG1 DACG0 DACBP R/W R ...
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... Bits 7-4 of register TCTL control the DVI PLL phase detector. The default value is recommended R/W R/W R TPPD 1 TPPD 0 CTL3 R/W R/W R CH7301C Symbol: HPD Address: 23h HPDD Reserved Reserved R/W R Symbol: TCTL Address: 31h CTL2 CTL1 ...
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... This register controls the voltage in the DVI PLL, use default settings for this register. 201-0000-056 Rev. 1.32, 5/24/2005 DVID0 DVII TPPSD1 TPPSD0 Reserved R/W R/W R R/W R/W R R/W R/W R CH7301C Symbol: TPCP Address: 33h TPCP0 R/W R Symbol: TPD Address: 34h TPFBD0 R/W R Symbol: TPVT Address: 35h 3 2 ...
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... This register is used for internal testing. The default value is recommended TPLPF1 TPLPF0 Reserved Reserved Reserved R/W R/W R <= 65MHz > 65MHz 08h 06h 16h 26h 60h A0h R/W R CH7301C Symbol: TPF Address: 36h Reserved R/W R Symbol: TCT Address: 37h R/W R/W R 201-0000-056 Rev. 1.32, ...
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... Power Management Register BIT: 7 SYMBOL: DVIP DVIL Reserved Reserved DACPD2 DACPD1 DACPD0 TYPE: R/W R/W DEFAULT: 0 Register PM controls which circuitry within the CH7301C is operating, according to Table 12 below. Table 12. Power Management 49h[7] 49h[6] 56h[0] 21h[0] 49h[3:1] 49h[0] Operating State 000 ...
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... CHRONTEL Version ID Register BIT: 7 SYMBOL: VID7 VID6 TYPE: R DEFAULT: 1 Register VID is a read only register containing the version ID number of the CH7301C. Device ID Register BIT: 7 SYMBOL: DID7 DID6 TYPE: R DEFAULT: 0 Register DID is a read only register containing the device ID number of the CH7301C. ...
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... Full scale output current Video level error I 3 DACs Enabled VDD I DVDDV (1.8V) current (15pF load) DVDDV I TOTAL PD 201-0000-056 Rev. 1.32, 5/24/2005 Description GND – 0.5 Min 3.1 3.1 3.1 1 Min 10 CH7301C Min Typ Max Units -0.5 5.0 VDD + 0.5 Indefinite 0 85 -65 150 150 260 245 225 Typ Max Units 3.3 3.6 3.3 3.6 3.3 3 ...
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... DATA HPDET inputs and GPIOx, VSYNC and HSYNC outputs. 24 Test Condition Min 1.0 GND-0.5 0.25 Vref+0.25 GND-0.5 DVDD=3.3V 2.7 DVDD=3.3V GND-0 0 3.3V 0 -0.4mA DVDD-0 3.2mA OL 201-0000-056 CH7301C Typ Max Unit 0.4 V VDD + 0 DVDD+0.5 V Vref-0.25 V VDD + 0.5 V 0.6 V 5 0.2 V Rev. 1.32, 5/24/2005 ...
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... XCLK f = 165MHz 75 XCLK f = 165MHz XCLK f = 165MHz XCLK f = 165MHz XCLK XCLK = XCLK* to 0.50 D[11:0 Vref D[11:0 Vref 0.50 to XCLK = XCLK* 15pF load VDDV = 3.3V 15pF load VDDV = 3.3V 50 CH7301C Typ Max Unit 165 MHz 242 ps 242 1.2 ns 150 1. ...
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... Hold Time: D[11:0 and DE to XCLK, XCLK XCLK & XCLK* rise/fall time w/15pF load t2 D[11:0 & DE rise/fall time w/ 15pF load VGA Line t2 CH7301C P0a P0b P1a P1b P2a P2b Min Typ Max Unit See Table 17 ...
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... Dimension B: Top Package body size may be smaller than bottom package size by as much as 0.15 mm. 3. Dimension B does not include allowable mold protrusions up to 0.25 mm per side. 201-0000-056 Rev. 1.32, 5/24/2005 SYMBOL 0.17 1.35 0.05 0.50 0.27 1.45 0.15 CH7301C LEAD CO-PLANARITY E .004 “ 0.45 0.09 0° 1.00 0.75 0.20 7° 27 ...
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... Description First official release of CH7301C datasheet, rev. 1.0 Edited Table 2 for DVI output resolutions Added ’Color space conversion and sync decode’ block. Added register 56h, bit 0 for YCrCb to RGB color space conversion. Added bit 5 for DVI embedded sync polarity control Updated DVI hotplug description ...
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... Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used as directed can reasonably expect to result in personal injury or death. Part number CH7301C-T CH7301C-T-TR CH7301C-TF CH7301C-TF-TR ©2004 Chrontel, Inc. All Rights Reserved. Printed in the U.S.A. 201-0000-056 Rev. 1.32, 5/24/2005 ...