ch7301c Chrontel, ch7301c Datasheet - Page 14

• Manufacturer Part Number: ch7301c
• Description: Ch7301 Dvi Transmitter
• Manufacturer: Chrontel

CHRONTEL
4.2 Registers Read/Write
Regarding the CH7301C registers read/write operation, please see applications note AN-41 for details.
All register bits not defined in the register map are reserved bits, and should be left at the default value.
Clock Mode Register
Bit 0 of register CM signifies the XCLK frequency. A value of ‘0’ is used when the XCLK is at the pixel frequency
(duel edge clocking mode) and a value of ‘1’ is used when the XCLK is twice the pixel frequency (single edge
clocking mode).
Bit 2 of register CM controls the phase of the XCLK clock input to the CH7301C. A value of ‘1’ inverts the XCLK
signal at the input of the device. This control is used to select which edge of the XCLK signal to use for latching
input data.
14
Table 8. Serial Port Register Map
Register
1Ch
1Dh
1Eh
1Fh
20h
21h
23h
31h
33h
34h
35h
36h
37h
48h
49h
4Ah
4Bh
56h
DEFAULT:
SYMBOL:
TYPE:
BIT:
Bit 7
Reserved
Reserved
GOENB1
Reserved
HPIE
Reserved
Reserved
TPPD3
DVID2
Reserved
Reserved
TPLPF3
Reserved
Reserved
DVIP
VID7
DID7
Reserved
Reserved Reserved Reserved Reserved Reserved
R/W
7
0
Reserved
DVIL
Bit 6
Reserved
GOENB0
DES
Reserved
Reserved
Reserved
TPPD2
DVID1
Reserved
Reserved
TPLPF2
Reserved
Reserved
VID6
DID6
Reserved
R/W
6
0
Bit 5
Reserved
Reserved
GPIOL1
Reserved
DVIT
Reserved
Reserved
TPPD1
DVID0
TPFFD1
Reserved
TPLPF1
Reserved
Reserved
Reserved
VID5
DID5
TMSYO
R/W
5
0
Bit 4
Reserved
Reserved
GPIOL0
VSP
Reserved
Reserved
Reserved
TPPD0
DVII
TPFFD0
Reserved
TPLPF0
Reserved
ResetIB
Reserved
VID4
DID4
Reserved
R/W
4
0
Bit 3
Reserved
XCMD3
HPIR
HSP
DACT2
SYNCO0
Reserved
CTL3
TPPSD1
TPFBD3
Reserved
Reserved
Reserved
ResetDB
DACPD2
VID3
DID3
Reserved
R/W
3
0
201-0000-056
Bit 2
MCP
XCMD2
Reserved
IDF2
DACT1
DACG1
HPDD
CTL2
TPPSD0
TPFBD2
Reserved
Reserved
Reserved
Reserved
DACPD1
VID2
DID2
Reserved
MCP Reserved
R/W
Symbol:
Address:
2
0
Bit 1
Reserved
XCMD1
Reserved
IDF1
DACT0
DACG0
Reserved
CTL1
Reserved
TPFBD1
Reserved
Reserved
Reserved
TSTP1
DACPD0
VID1
DID1
Reserved
Rev. 1.32,
R/W
CH7301C
1
0
Bit 0
XCM
XCMD0
Reserved
IDF0
SENSE
DACBP
Reserved
CTL0
TPCP0
TPFBD0
Reserved
Reserved
Reserved
TSTP0
FPD
VID0
DID0
T_RGB
CM
1Ch
5/24/2005
XCM
R/W
0
0