ch7301c Chrontel, ch7301c Datasheet - Page 15

• Manufacturer Part Number: ch7301c
• Description: Ch7301 Dvi Transmitter
• Manufacturer: Chrontel

CHRONTEL
Input Clock Register
XCMD[3:0] (bits 3-0) of register IC control the delay applied to the XCLK signal before latching input data D[11:0] per
the following table. t
GPIO Control Register
201-0000-056
Table 9. Delay applied to XCLK before latching input data D[11:0]
DEFAULT:
DEFAULT:
SYMBOL:
SYMBOL:
XCMD3
TYPE:
TYPE:
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
BIT:
BIT:
GOENB1 GOENB0 GPIOL1 GPIOL0
Reserved Reserved Reserved Reserved XCMD3 XCMD2 XCMD1
XCMD2
Rev. 1.32,
R/W
R/W
STEP
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
7
0
7
1
is given in Table 17.
XCMD1
5/24/2005
R/W
R/W
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
6
1
6
1
XCMD0
R/W
R/W
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
5
0
5
0
Adjust phase of Clock relative to Data
0 * t
1 * t
2 * t
3 * t
4 * t
5 * t
6 * t
7 * t
0 * t
1 * t
2 * t
3 * t
4 * t
5 * t
6 * t
7 * t
R/W
R/W
STEP
STEP
STEP
STEP
STEP
STEP
STEP
STEP
STEP
STEP
STEP
STEP
STEP
STEP
STEP
STEP
4
0
4
0
, XCLK ahead of Data
, XCLK ahead of Data
, XCLK ahead of Data
, XCLK ahead of Data
, XCLK ahead of Data
, XCLK ahead of Data
, XCLK ahead of Data
, XCLK ahead of Data
, XCLK behind Data
, XCLK behind Data
, XCLK behind Data
, XCLK behind Data
, XCLK behind Data
, XCLK behind Data
, XCLK behind Data
, XCLK behind Data
HPIR Reserved Reserved
R/W
R/W
3
0
3
1
R/W
R/W
Symbol:
Address:
Symbol:
Address:
2
0
2
0
R/W
R/W
CH7301C
1
0
1
0
IC
1Dh
GPIO
1Eh
Reserved
XCMD0
R/W
R/W
15
0
0
0
0