ch7301c Chrontel, ch7301c Datasheet - Page 13

• Manufacturer Part Number: ch7301c
• Description: Ch7301 Dvi Transmitter
• Manufacturer: Chrontel

CHRONTEL
4. R
The CH7301C is controlled via a serial port. The serial port bus uses only the SPC clock to latch data into registers, and
does not use any internally generated clocks so that the device can be written to in all power down modes. The device
retains all register states.
4.1 Control Registers Map
The controls are listed below, divided into three sections: general controls, input / output controls, DVI controls. A
register map and register description follows.
• General Controls
ResetIB
ResetDB
PD[7:0]
VID[7:0]
DID[7:0]
TSTP[1:0]
• Input/Output Controls
XCM
XCMD[3:0]
MCP
IDF[2:0]
GPIOL[1:0]
GOENB[1:0]
SYNCO[1:0]
DACG[1:0]
DACBP
DES
HSP
VSP
T_RGB
• DVI Controls
CTL[3:0]
DVID[2:0]
DVIP
DVIL
DVIT
HPDD
HPIE
HPIR
TPFBD[3:0]
TPCP[1:0]
TPFFD[1:0]
TPPSD[1:0]
TPLPF[3:0]
DVII
TMSYO
201-0000-056
EGISTER
Software serial reset
Software datapath reset
Power down controls (DVIP, DVIL, TVD, DACPD[2:0], FDP)
Version ID register
Device ID register
Enable/select test pattern generation (color bar, ramp)
XCLK 1X, 2X select
Delay adjust between XCLK and D[11:0]
XCLK polarity control
Input data format
Read or write level for GPIO pins
Direction control for GPIO pins
Enables/selects sync output for RGB and bypass modes
DAC gain control
DAC bypass
Decode embedded sync
H sync polarity control
V sync polarity control
YCrCb to RGB enable
DVI Control Inputs
DVI transmitter drive strength control
DVI Power Down Control
DVI Power Down Control
Hot Plug Detection Pin Level
Hot Plug Detection Disable
Hot Plug Interrupt Enable on GPIO[1]
Hot Plug Interrupt Reset
DVI PLL feed back divider
DVI PLL charge pump trim
DVI PLL feed forward divider
DVI PLL post scale divider
DVI PLL low pass filter
DVI output invert
DVI Sync Direction
Rev. 1.32,
C
ONTROL
5/24/2005
CH7301C
13