ch7304 Chrontel, ch7304 Datasheet - Page 10

• Manufacturer Part Number: ch7304
• Description: Ch7304 Single Channel Lvds Transmitter
• Manufacturer: Chrontel

CHRONTEL
2.2.2
The CH7304 has a dither engine that can convert the 24-bit pixel data to 18-bit pixel data for better image quality on 18-
bit panels. Maximum pixel rate supported is 100M Pixels / sec.
2.2.3
The CH7304 conforms to SPWG’s requirements on power sequencing. The timing specification shown in Figure 5 is a
superset of the requirements dictated by the SPWG specification. The power sequencing block consists of a state
machine and 5 hardware timers, which are programmable through the serial port to suit requirements by different panels.
It provides 2 signals ENAVDD and ENABKL to the LCD panel.
Power-on sequence begins when the LVDS software registers are set properly via the serial port and the internal PLL
lock detection circuit and the internal Sync detection circuits (see Section 2.2.4) indicate that HSYNC, VSYNC and
XCLK are stable. Note that the BKLEN bit (Register 66h) must be set in order for the ENABKL signal to be asserted.
Power-off sequence begins when any detection circuits indicate an instability in the timing signals (see Section 2.2.4), or
through software programming. Once the power-off sequence starts, the internal state machine will complete the
sequence and the power-on sequence is allowed only after T5 is passed.
When the LVDS output clock and data signals become invalid, these outputs are tri-stated or grounded depending on the
value of the LODP bit.
2.2.4
The LCD panel can be damaged if HSYNC is absent from the LVDS link. This situation can happen when there is a
catastrophic failure in the PC or the graphics system. The CH7304 is designed to prevent damage to the panel under such
a failure. If the system fails, the CH7304 does not expect any software instruction from the graphics controller to power
down the panel. Detection circuits are used to monitor the three timing signals – HSYNC, VSYNC and XCLK. If any
one, combination of, or all of these signals becomes unstable, the CH7304 will commence Power Down Sequencing
according to Section 2.2.3. A description of these detection circuits is shown in Figure 6.
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Table 6: Power Sequencing
Dithering
Power Sequencing
Panel Protection
LVDS Clocks
LVDS_RDY
LVDS Data
ENEXBUF
ENAVDD
(Internal)
ENABKL
T1
T2
T3
T4
T5
T1
T2
Figure 5: Power Sequencing
Valid Clock
Valid Data
2-1600 ms
2-512 ms
2-256 ms
2-256 ms
2-512 ms
Range
T3
T4
Tristate or GND
Tristate or GND
201-0000-053
T5
Increment
50ms
1 ms
1 ms
2ms
2ms
Rev. 1.31,
CH7304
6/14/2006