ch7304 Chrontel, ch7304 Datasheet - Page 16

• Manufacturer Part Number: ch7304
• Description: Ch7304 Single Channel Lvds Transmitter
• Manufacturer: Chrontel

CHRONTEL
Input Data Format Register
IDF[2:0] (bits 2-0) of Register IDF select the input data format for the input. See Section 2.1.5 for a listing of available
formats.
IBS (bit 7) of Register IDF selects the data and clock input buffer type for the D[11:0] data according to the following
table:
16
DEFAULT:
SYMBOL:
TYPE:
XCMD3
BIT:
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
IBS
0
1
R/W
IBS
7
1
XCMD2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Reserved Reserved Reserved Reserved
D[11:0] Input Buffer Type
CMOS, single ended type for clock and data
Differential (clock) and comparator (data) type
Table 8: Delay applied to XCLK before latching input data
R/W
6
0
XCMD1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Table 9: D[11:0] Input Buffer Type Selection
R/W
5
0
XCMD0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
R/W
4
0
Adjust phase of Clock relative to Data
0 * t
1 * t
2 * t
3 * t
4 * t
5 * t
6 * t
7 * t
0 * t
1 * t
2 * t
3 * t
4 * t
5 * t
6 * t
7 * t
STEP
STEP
STEP
STEP
STEP
STEP
STEP
STEP
STEP
STEP
STEP
STEP
STEP
STEP
STEP
STEP
R/W
3
0
, XCLK ahead of Data
, XCLK ahead of Data
, XCLK ahead of Data
, XCLK ahead of Data
, XCLK ahead of Data
, XCLK ahead of Data
, XCLK ahead of Data
, XCLK ahead of Data
, XCLK behind Data
, XCLK behind Data
, XCLK behind Data
, XCLK behind Data
, XCLK behind Data
, XCLK behind Data
, XCLK behind Data
, XCLK behind Data
201-0000-053
Symbol:
Address:
IDF2
R/W
2
0
Rev. 1.31,
IDF1
IDF
1Fh
R/W
1
0
CH7304
6/14/2006
IDF0
R/W
0
0