ch7304 Chrontel, ch7304 Datasheet - Page 15

• Manufacturer Part Number: ch7304
• Description: Ch7304 Single Channel Lvds Transmitter
• Manufacturer: Chrontel

CHRONTEL
3.3
Clock Detect Defeat
CLKDETD (bit 2) of Register CDD controls the XCLK detection circuit. When CLKDETD is ‘1’ the XCLK detection
circuit is turned off, when CLKDETD is 0 the XCLK detection is on.
Clock Mode Register
XCM (bit 0) of Register CM signifies the XCLK frequency for the D[11:0] input. A value of ‘0’ is used when XCLK is
at the pixel frequency (dual edge clocking mode) and a value of ‘1’ is used when XCLK is twice the pixel frequency
(single edge clocking mode).
MCP (bit 2) of Register CM controls the phase of the XCLK clock input for the D[11:0] input. A value of ‘1’ inverts
the XCLK signal at the input of the device. This control is used to select which edge of the XCLK signal to use for
latching input data.
Input Clock Register
XCMD[3:0] (bits 3-0) of Register IC control the delay applied to the XCLK signal before latching input data D[11:0]
per the following table. t
201-0000-053
DEFAULT:
DEFAULT:
DEFAULT:
SYMBOL:
SYMBOL:
SYMBOL:
TYPE:
TYPE:
TYPE:
Control Registers Description
BIT:
BIT:
Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved
R/W
R/W
R/W
Rev. 1.31, 6/14/2006
7
0
7
0
7
0
STEP
is given in Section 4.5.
R/W
R/W
R/W
6
0
6
0
6
1
R/W
R/W
R/W
5
0
5
0
5
0
R/W
R/W
R/W
4
0
4
0
4
0
R/W
XCMD3 XCMD2 XCMD1 XCMD0
R/W
3
0
R/W
3
0
3
1
CLKDETD
Symbol:
Address:
Symbol:
Address:
Symbol:
Address:
R/W
MCP
R/W
R/W
2
0
2
0
2
0
Reserved
Reserved Reserved
R/W
R/W
CDD
14h
CM
1Ch
IC
1Dh
R/W
1
0
1
1
1
0
CH7304
XCM
R/W
R/W
R/W
0
0
0
0
0
0
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