ch7304 Chrontel, ch7304 Datasheet - Page 20

• Manufacturer Part Number: ch7304
• Description: Ch7304 Single Channel Lvds Transmitter
• Manufacturer: Chrontel

CHRONTEL
BKLEN (bit 5) of the LPMC register enables the panel backlight.
SYNCST(bit 6) of the LPMC register is the Hsync and Vsync stability status bit. Refer to Section 2.2.4.
Power Sequencing T1
This register defines Power On time (T1), the time duration between LVDS_RDY (internal signal) to valid LVDS Clock
and Data. The entire bit field, TPON[8:0], is comprised of these bits TPON[7:0] plus TPON8 contained in the PST2
Power Sequencing T2 register (Register 68h, bit 7). Refer to Figure 5 and Table 6 in Section 2.2.3. The range of T1 is
2ms to 512ms in increments of 1ms.
Power Sequencing T2
TPBLE[6:0] (bits 6:0) of Register PST2 define the Back Light Enable time (T2), the waiting time after valid LVDS
Clock and Data before enabling the LVDS panel back light. Refer to Figure 5 and Table 6 in Section 2.2.3. The range
of T2 is 2ms to 256ms in increments of 2ms.
TPON8 (bit 7) of Register PST2 defines the MSB of the Power On time (T1). The entire bit field, TPON[8:0], is
comprised of this bit, TPON8, plus TPON[7:0] contained in the Power Sequencing T1 register (Register 67h). Refer to
the description of the PST1 register (Register 67h) for more information.
Power Sequencing T3
20
DEFAULT:
DEFAULT:
DEFAULT:
SYMBOL:
SYMBOL:
SYMBOL:
BKLEN
SYNCST
TYPE:
TYPE:
TYPE:
BIT:
BIT:
BIT:
TP0FF8 TPBLD6 TPBLD5 TPBLD4 TPBLD3 TPBLD2 TPBLD1 TPBLD0
= 0 => Disable Backlight
= 1 => Enable Backlight
= 0 => Hsync or Vsync are not stable
= 1 => Hsync and Vsync are stable
TPON7
TPON8
R/W
R/W
R/W
0
7
0
7
0
7
TPBLE6 TPBLE5 TPBLE4 TPBLE3 TPBLE2 TPBLE1 TPBLE0
TPON6
R/W
R/W
R/W
6
0
6
0
6
0
TPON5
R/W
R/W
R/W
5
0
5
0
5
0
TPON4
R/W
R/W
R/W
4
0
4
0
4
0
TPON3
R/W
R/W
R/W
3
0
3
0
3
0
201-0000-053
Symbol:
Address:
Symbol:
Address:
Symbol:
Address:
TPON2
R/W
R/W
R/W
0
2
2
0
2
0
Rev. 1.31,
TPON1
R/W
PST1
67h
PST2
68h
PST3
69h
R/W
R/W
1
0
1
0
1
0
CH7304
TPON0
6/14/2006
R/W
R/W
R/W
0
0
0
0
0
0