UPD705100GJ-100-8 NEC [NEC], UPD705100GJ-100-8 Datasheet - Page 35

no-image

UPD705100GJ-100-8

Manufacturer Part Number
UPD705100GJ-100-8
Description
V830TM 32-BIT MICROCONTROLLER
Manufacturer
NEC [NEC]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD705100GJ-100-8EU
Manufacturer:
NEC
Quantity:
300
Part Number:
UPD705100GJ-100-8EU
Manufacturer:
NEC
Quantity:
20 000
Instruction
JAL
JMP
JR
LD.B
LD.H
LD.W
LDSR
MAC3
disp26
[reg1]
disp26
disp16[reg1],
reg2
disp16[reg1],
reg2
disp16[reg1],
reg2
reg2, regID
reg1, reg2,
reg3
Operand(s)
IV
I
IV
VI
VI
VI
II
VIII
Format
CY
-
-
-
-
-
-
-
OV
-
-
-
-
-
-
-
S
-
-
-
-
-
-
-
Z
-
-
-
-
-
-
-
Jump and link. The sum of the current PC
and 4 is written into r31. disp26, sign-extended
to a word, is added to the PC and the sum is
set to the PC for control transfer. Bit 0 of
disp26 is masked.
Indirect unconditional branch via register.
Control is passed to the address designated by
reg1. Bit 0 of the address is masked to 0.
Unconditional branch. disp26, sign-extended to
a word, is added to the current PC and control
is passed to the address specified by that sum.
Bit 0 of disp26 is masked to 0.
Byte load. disp16, sign-extended to a word,
is added to reg1 to produce an unsigned 32-bit
address. A byte of data is read from the
produced address, sign-extended to a word,
then written into reg2.
Halfword load. disp16, sign-extended to a word,
is added to reg1 to produce an unsigned 32-bit
address. A halfword of data is read from the
produced address, sign-extended to a word,
then written into reg2. Bit 0 of the unsigned
32-bit address is masked to 0.
Word load. disp16, sign-extended to a word,
is added to reg1 to produce an unsigned 32-bit
address. A word of data is read from the
produced address, then written into reg2. Bits 0
and 1 of the unsigned 32-bit address are
masked to 0.
Load into system register. The contents of
reg2 are set in the system register identified by
the system register number (regID).
Saturatable operation on signed 32-bit operands.
reg1 and reg2 are multiplied together as signed
integers and the product is added to reg3.
[If no overflow has occurred:]
[If an overflow has occurred:]
The result is stored in reg3.
The SAT bit is set. If the result is positive,
the positive maximum is written into reg3; if
the result is negative, the negative maximum
is written into reg3.
Function
PD705100
35

Related parts for UPD705100GJ-100-8