UPD705100GJ-100-8 NEC [NEC], UPD705100GJ-100-8 Datasheet - Page 45

• Manufacturer Part Number: UPD705100GJ-100-8
• Description: V830TM 32-BIT MICROCONTROLLER
• Manufacturer: NEC [NEC]

(2) Reset timing
RESET hold time
(relative to V
Clock period (when reset)
Clock high level width (when reset)
Clock low level width (when reset)
RESET set time
(relative to BCLK , active)
RESET set time
(relative to BCLK , inactive)
RESET hold time (relative to BCLK )
RESET pulse low level width
RESET hold time
(relative to V
Clock period (when reset)
Clock high level width (when reset)
Clock low level width (when reset)
RESET set time
(relative to BCLK , active)
RESET set time
(relative to BCLK , inactive)
RESET hold time (relative to BCLK )
RESET pulse low level width
Notes 1. At power-on or return from stop mode
Remarks 1. The reset signal need not satisfy t
Notes 1. At power-on or return from stop mode
Remarks 1. The reset signal need not satisfy t
(a) When the internal operating frequency is 75 to 100 MHz
(b) When the internal operating frequency is 48 to 100 MHz
2. Other than the conditions stated in Note 1.
2. Other than the conditions stated in Note 1.
Parameter
Parameter
DD
DD
2. t
2. t
VALID)
VALID)
WRL
WRL
(
(
13
13
) is the number of clock cycles (t
) is the number of clock cycles (t
10
11
12
13
10
11
12
13
8
9
8
9
6
7
6
7
Symbol
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
HVR
CYKR
KKHR
KKLR
SRKF
SRKR
HKR
WRL
HVR
CYKR
KKHR
KKLR
SRKF
SRKR
HKR
WRL
Note 1
Note 2
Note 1
Note 2
SRKF
SRKF
Conditions
Conditions
(
(
10
10
CYKR
CYKR
) or t
) or t
) counted after the BCLK signal has settled.
) counted after the BCLK signal has settled.
SRKR
SRKR
MIN.
MIN.
(
(
When
When
30
10
10
10
20
30
10
10
10
20
0
8
8
0
0
8
8
0
11
11
), provided it is within t
), provided it is within t
= 3f
= 3f
MAX.
MAX.
62.5
40
2
2
MIN.
MIN.
When
When
20
10
20
20
10
20
0
5
5
8
8
0
0
5
5
8
8
0
= 2f
= 2f
MAX.
MAX.
26.7
41.6
HVR
HVR
2
2
PD705100
(
(
6
6
).
).
t
t
Unit
Unit
CYKR
CYKR
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
45