UPD705100GJ-100-8 NEC [NEC], UPD705100GJ-100-8 Datasheet - Page 39

• Manufacturer Part Number: UPD705100GJ-100-8
• Description: V830TM 32-BIT MICROCONTROLLER
• Manufacturer: NEC [NEC]

Instruction
SHR
SHRD3
ST.B
ST.H
ST.W
STBY
STSR
SUB
TRAP
reg1, reg2
imm5, reg2
reg1, reg2,
reg3
reg2,
disp16[reg1]
reg2,
disp16[reg1]
reg2,
disp16[reg1]
regID,reg2
reg1,reg2
vector
Operand(s)
I
II
VIII
VI
VI
VI
IX
II
I
II
Format
CY
-
-
-
-
-
-
-
OV
0
0
-
-
-
-
-
-
-
S
-
-
-
-
-
-
-
Z
-
-
-
-
-
-
-
Logical right shift. reg2 is logically shifted to
the right by the displacement specified by the
low-order five bits of reg1 (0 is put on the MSB).
The result is written into reg2.
Logical right shift. reg2 is logically shifted to
the right by the displacement specified by imm5,
zero-extended to a word. The result is written
into reg2.
Right shift of concatenation. The 64 bits
consisting of reg3 (high order) and reg2
(low order) are logically shifted to the right by
the displacement specified by the low-order five
bits of reg1. The low-order 32 bits of the result
are written into reg3.
Byte store. disp16, sign-extended to a word,
is added to reg1 to produce an unsigned 32-bit
address. The low-order one byte of data in reg2
is stored at the resulting address.
Halfword store. disp16, sign-extended to a
word, is added to reg1 to produce an unsigned
32-bit address. The low-order two bytes of the
data in reg2 are stored at the resulting address.
Bit 0 of the unsigned 32-bit address is masked
to 0.
Word store. disp16, sign-extended to a word,
is added to reg1 to produce an unsigned 32-bit
address. The word of data in reg2 is stored at
the resulting address. Bits 0 and 1 of the
unsigned 32-bit address are masked to 0.
Processor stop. The processor is placed in
stop mode.
System register store. The contents of the
system register identified by the system
register number (regID) are set in reg2.
Subtraction. reg1 is subtracted from reg2.
The difference is written into reg2.
Software trap. The return PC and PSW are
saved in the system registers:
PSW.EP = 1
PSW.EP = 0
The exception code is set in the ECR:
PSW.EP = 1
PSW.EP = 0
PSW flags are set:
PSW.EP = 1
PSW.EP = 0
Program execution jumps to the trap handler
address corresponding to the trap vector (0-31)
specified by vector and begins exception
handling.
Save in FEPC, FEPSW
Save in EIPC, EIPSW
Set in FECC
Set in EICC
Set NP and ID
Set EP and ID
Function
PD705100
39