pll2109x Samsung Semiconductor, Inc., pll2109x Datasheet
pll2109x
Related parts for pll2109x
pll2109x Summary of contents
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... FSPLL GENERAL DESCRIPTION The pll2109x is a Phase Locked Loop(PLL) frequency synthesizer. The PLL provides frequency multiplication capabilities. Its output clock frequency FOUT is related to the input clock frequency FIN by the following equation: s FOUT = (m FIN where FOUT is the output clock frequency. FIN is the input clock frequency and s are the values for programmable dividers ...
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... PLL2109X (PRELIMINARY) FUNCTIONAL BLOCK DIAGRAM FIN Pre-Divider (P) 6b M[7:0] P[5:0] S[1:0] PWRDN AVDD12A 2 AVDD12D AVSS12D Fin/p UP Phase Frequency Detector Fvco /m DN Main -Divider (M) 8b AVSS12A VABB Figure 1. Block Diagram 100MHZ ~ 500MHZ FSPLL FILTER Loop Loop Charge Charge Pump Pump Filter Filter Voltage Fvco Controlled ...
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... Analog / Digital bulk bias DI PLL clock input DO 100MHz ~ 500MHz clock output AO The external loop filter capacitor should be connected between FILTER and analog ground DI Power down PWRDN is high, power down mode is enabled. DI 6-bit programmable pre-divider. DI 8-bit programmable main-divider. DI 2-bit programmable post-scaler. PLL2109X (PRELIMINARY) Pin Description 3 ...
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... PLL2109X (PRELIMINARY) CORE CONFIGURATION FIN FIN PWRDN PWRDN M[7:0] M[7:0] P[5:0] P[5:0] S[1:0] S[1:0] ABSOLUTE MAXIMUM RATING Characteristics Supply voltage Storage temperature NOTES: 1. Absolute maximum rating specifies the values beyond which the device may be damaged permanently. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Each condition value is applied with the other values kept within the following operating conditions and function operation under any of these conditions is not implied ...
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... Fvco 200 Fout 100 – – Z JCC T – Z JCC T – Z JCC T – Z JCC PLL2109X (PRELIMINARY) Max Unit Remark +0 Capacitor tolerance ( 5 Min Typ Max 1.14 1.20 1.26 0.7VDD – – – – 0.3VDD – – 3 – – TBD Typ Max – ...
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... FUNCTIONAL DESCRIPTION A PLL is the circuit synchronizing an output signal (generated by a VCO) with a reference or input signal in frequency as well as in phase. The pll2109x can provide frequency multiplication capabilities, but does not support functions such as deskew and phase synchronization between Fin and Fout. PLL2109X consists of the following basic blocks. ...
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... Method and S pins are bypassed to the external port, and you can control each port directly undesirable to connect P[5:0], M[7:0] and S[1:0] to the internal power or ground directly because of ESD issue. 1.2V 1.7nF(chip cap) NOTE: 10uF electrolytic capacitor : Unless otherwise specified : 0.1uF ceramic capacitor Unless otherwise specified FILTER pll2109x PLL2109X (PRELIMINARY) GND Fout 7 ...
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... PLL2109X (PRELIMINARY) CORE LAYOUT GUIDE 1. The Digital power(AVDD12D, AVSS12D) and the analog power(AVDD12A, AVSS12A) must be dedicated to PLL only and separated. Please consult PLL dedicated I/O assign with SEC application engineer. 2. The FOUT and FILTER pins and routings must be placed far from the internal signals in order to avoid cross- talk ...
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... PHANTOM CELL INFORMATION Pins of the core can be assigned externally(package pins) or internally(internal ports) depending on design methods. — The term "external" implies that the pins should be assigned externally like power pins. — The term "internal/external" implies that those pins are user dependent. pll2109x PLL2109X (PRELIMINARY) 9 ...
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... PLL2109X (PRELIMINARY) PIN LAYOUT GUIDE Pin Name Pin Usage AVDD12D External AVSS12D External AVDD12A External AVSS12A External VABB External FIN External FOUT External/Internal – Do not place noisy, high frequency and high power consuming circuitry FILTER External PWRDN Internal /External M[7] ~ M[0] Internal/External P[5] ~ P[0] ...
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... Tracking Jitter (TJT) If you have another special request, please describe below. Customer 100M ~ 200M 200M ~ 300M 300M ~ 400M 400M ~ 500M 100M ~ 200M 200M ~ 300M 300M ~ 400M 400M ~ 500M Customer PLL2109X (PRELIMINARY) SEC Unit 0.13um CMOS V 1.2 0. MHz 100 ~ 500 MHz TBD ...
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... PLL2109X (PRELIMINARY) JITTER DEFINITION Period Jitter Period jitter is the maximum deviation of output clock's transition from its ideal position. Cycle-to-Cycle Jitter Cycle-to-cycle jitter is the maximum deviation of output clock's transition from its corresponding position of the previous cycle. Fout Long-Term Jitter Long-term jitter is the maximum deviation of output clock' transition from its ideal position, after many cycles. ...
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... FSPLL Tracking Jitter Tracking jitter is the maximum deviation of output clock(FOUT)'s transition from input clock (FIN) position. Trigger Fin Delay Fout TJT PLL2109X (PRELIMINARY) 13 ...