pll2109x Samsung Semiconductor, Inc., pll2109x Datasheet - Page 10

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pll2109x

Manufacturer Part Number
pll2109x
Description
Description = PLL2109X 100MHz ~ 500MHz FSPLL ;; Function = FSPLL ;; Configuration = 100~500MHz FSPLL ;; Library Type = STD150 ;; Characteristic = 1.2V/3mA
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
PLL2109X (PRELIMINARY)
PIN LAYOUT GUIDE
10
AVDD12D
AVSS12D
AVDD12A
AVSS12A
VABB
FIN
FOUT
FILTER
PWRDN
M[7] ~ M[0]
P[5] ~ P[0]
S[1] ~ S[0]
Pin Name
External/Internal – Do not place noisy, high frequency and high power consuming circuitry
Internal/External
Internal/External
Internal/External
Pin Usage
/External
External
External
External
External
External
External
External
Internal
– Use dedicated power/ground pins for PLL
– Power cuts are required to provide on-chip isolation
– Use good power and ground source on board
– Do not place noisy, high frequency and high power consuming circuitry
– Use proper low jitter reference clock
– Internal routing path should be as short as possible. This will minimize
– FOUT signals should not be crossed by any signals and should not run
– Do not place the noisy, high frequency and high power consuming circuitry
– Ground shielding is needed for internal routing path.
– FILTER routing path should not be crossed by any other signals and
– External loop filter pin should be placed between analog power and
– External loop filter components and internal routing should be as short as
pads near the FIN pin.
pads near the FOUT pin.
loading effect.
next to digital signals. This will minimize capacitive coupling between the
two signals.
pads near the FILTER.
should not be placed next to digital signals.
ground to avoid stray coupling outside the chip and magnetic coupling via
bond wires.
possible.
between dedicated PLL power/ground and all other power/ground
Pin Layout Guide
100MHZ ~ 500MHZ FSPLL

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