A1280DX-1CQB ACTEL [Actel Corporation], A1280DX-1CQB Datasheet - Page 11

• Manufacturer Part Number: A1280DX-1CQB
• Description: Integrator Series FPGAs: 1200XL and 3200DX Families
• Manufacturer: ACTEL [Actel Corporation]

I n t e g r a t o r S e r i e s F PG A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s
Table 1 • IEEE 1149.1 BST Signals
JTAG
All 3200DX devices are IEEE 1149.1 (JTAG) compliant.
3200DX devices offer superior diagnostic and testing
capabilities by providing JTAG and probing capabilites.
These functions are controlled through the special JTAG
pins in conjunction with the program fuse.
JTAG fuse programmed:
• TCK must be terminated—logical high or low doesn’t
• TDI, TMS may float or at logical high (internal pull-up is
• TDO may float or connect to TDI of another device (it’s an
JTAG fuse not programmed:
• TCK, TDI, TDO, TMS are user I/O. If not used, they will be
BST Instructions
Boundary scan testing within the 3200DX devices is
controlled by a Test Access Port (TAP) state machine. The
TAP controller drives the three-bit instruction register, a
bypass register, and the boundary scan data registers within
the device. The TAP controller uses the TMS signal to
control the testing of the device. The BST mode is
determined by the bitstream entered on the TMS pin.
Table 2
3200DX devices.
Reset
The TMS pin is equipped with an internal pull-up resistor.
This allows the TAP controller to remain in or return to the
Test-Logic-Reset state when there is no input or when a
logical 1 is on the TMS pin. To reset the controller, TMS
must be HIGH for at least five TCK cycles.
When a device is operating in BST mode, four I/O pins are
used for the TDI, TDO, TMS, and TCLK signals. An active
reset (nTRST) pin is not supported; however, the 3200DX
contains power-on circuitry which automatically resets the
BST circuitry upon power-up. The following table
summarizes the functions of the BST signals.
Signal
TDI
TDO
TMS
TCK
matter (to avoid floating input)
present)
output)
configured as tristated output.
describes the test instructions supported by the
Name
Test Data In
Test Data Out
Test Mode Select
Test Clock
Function
Serial data input for BST instructions and
data. Data is shifted in on the rising edge
of TCK.
Serial data output for BST instructions
and test data.
Serial data input for BST mode. Data is
shifted in on the rising edge of TCK.
Clock signal to shift the BST data into
the device.
Discontinued – v3.0
Table 2 • BST Instructions
JTAG BST Instructions
JTAG BST testing within the 3200DX devices is controlled
by a Test Access Port (TAP) state machine. The TAP
controller drives the three-bit instruction register, a bypass
register, and the boundary scan data registers within the
device. The TAP controller uses the TMS signal to control
the JTAG testing of the device. The JTAG test mode is
determined by the bitstream entered on the TMS pin. The
table in the next column describes the JTAG instructions
supported by the 3200DX.
Design Tool Support ActionProbe
If a device has been successfully programmed and the
security fuse has not been programmed, any internal logic
or I/O module output can be observed in real time using the
ActionProbe circuitry, the PRA and/or PRB pins, and Actel’s
Silicon Explorer diagnostic and debug tool kit.
Test Mode
EXTEST
SAMPLE/
PRELOAD
JPROBE
USER
INSTRUCTION
HIGH Z
CLAMP
BYPASS
Code
000
001
011
100
101
110
111
Description
Allows the external circuitry and
board-level interconnections to be tested
by forcing a test pattern at the output pins
and capturing test results at the input
pins.
Allows a snapshot of the signals at the
device pins to be captured and examined
during device operation.
A private instruction allowing the user to
connect Actel’s Micro Probe registers to
the test chain.
Allows the user to build
application-specific instructions such as
RAM READ and RAM WRITE.
Refer to the IEEE Standard 1149.1
specification.
Refer to the IEEE Standard 1149.1
specification.
Enables the bypass register between the
TDI and TDO pins. The test data passes
through the selected device to adjacent
devices in the test chain.
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