A1280DX-1CQB ACTEL [Actel Corporation], A1280DX-1CQB Datasheet - Page 55

• Manufacturer Part Number: A1280DX-1CQB
• Description: Integrator Series FPGAs: 1200XL and 3200DX Families
• Manufacturer: ACTEL [Actel Corporation]

I n t e g r a t o r S e r i e s F PG A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s
P i n D e s c r i p ti o n s
CLKA, CLKB Clock A and Clock B (Input)
TTL clock inputs for clock distribution networks. The clock
input is buffered prior to clocking the logic modules. This
pin can also be used as an I/O.
DCLK
TTL clock input for diagnostic probe and device
programming. DCLK is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
GND
Input LOW supply voltage.
I/O
I/O pin functions as an input, output, three-state or
bidirectional buffer. Input and output levels are compatible
with standard TTL and CMOS specifications. Unused I/O
pins are automatically driven LOW by the Designer Series
software for XL devices and are automatically tristated for
DX devices.
MODE
The MODE pin controls the use of multi-function pins
(DCLK, PRA, PRB, SDI, TDO). When the MODE pin is HIGH,
the special functions are active. To provide ActionProbe
capability, the MODE pin should be terminated to GND
through a 10K resistor so the MODE pin can be pulled HIGH
when required.
NC
This pin is not connected to circuitry within the device.
These pins can be driven to any voltage or can be left
floating with no effect on the operation of the device.
PRA, I/O
The Probe A pin is used to output data from any
user-defined design node within the device. This
independent diagnostic pin is used in conjunction with the
Probe B pin to allow real-time diagnostic output of any
signal path within the device. The Probe A pin can be used
as a user-defined I/O when debugging has been completed.
The pin's probe capabilities can be permanently disabled to
protect programmed design confidentiality. PRA is active
when the MODE pin is HIGH. This pin functions as an I/O
when the MODE pin is LOW.
Diagnostic Clock (Input)
Ground (Input)
Input/Output (Input, Output)
Mode (Input)
No Connection
Probe A (Output)
Discontinued – v3.0
PRB, I/O
The Probe B pin is used to output data from any
user-defined design node within the device. This
independent diagnostic pin is used in conjunction with the
Probe A pin to allow real-time diagnostic output of any
signal path within the device. The Probe B pin can be used
as a user-defined I/O when debugging has been completed.
The pin’s probe capabilities can be permanently disabled to
protect programmed design confidentiality. PRB is active
when the MODE pin is HIGH. This pin functions as an I/O
when the MODE pin is LOW.
QCLKA,B,C,D Quadrant Clock (Input/Output)
These four pins are the quadrant clock inputs. When not
used as a register control signal, these pins can function as
general purpose I/O.
SDO
Serial data output for diagnostic probe and device
programming. SDO is active when the MODE pin is HIGH.
This pin functions as an I/O when MODE pin is LOW.
SDI
Serial data input for diagnostic probe and device
programming. SDI is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
TCK
Clock signal to shift the JTAG data into the device. This pin
functions as an I/O when the JTAG fuse is not programmed.
TDI
Serial data input for JTAG instructions and data. Data is
shifted in on the rising edge of TCLK. This pin functions as
an I/O when the JTAG fuse is not programmed.
TDO
Serial data output for JTAG instructions and test data. This
pin functions as an I/O when the JTAG fuse is not
programmed.
TMS
Serial data input for JTAG test mode. Data is shifted in on
the rising edge of TCLK. This pin functions as an I/O when
the JTAG fuse is not programmed.
V
Input HIGH supply voltage.
Note:
CC
TCK, TDI, TDO, TMS are only available on devices
containing JTAG circuitry.
Probe B (Output)
Serial Data (Output)
Serial Data Input (Input)
Supply Voltage (Input)
Test Clock
Test Data In
Test Data Out
Test Mode Select
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