A1280DX-1CQB ACTEL [Actel Corporation], A1280DX-1CQB Datasheet - Page 31

• Manufacturer Part Number: A1280DX-1CQB
• Description: Integrator Series FPGAs: 1200XL and 3200DX Families
• Manufacturer: ACTEL [Actel Corporation]

I n t e g r a t o r S e r i e s F PG A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s
A 1 2 40 X L T i m i n g C h ar a ct e r i s t i c s
( Wo r s t -C as e C o m m erci al C o n di t io ns , V
Notes:
1.
2.
3.
4.
5.
Parameter
Logic ModulePropagation Delays
t
t
t
t
Predicted Routing Delays
t
t
t
t
t
Sequential Timing Characteristics
t
t
t
t
t
t
t
t
t
t
t
f
PD1
CO
GO
RS
RD1
RD2
RD3
RD4
RD8
SUD
HD
SUENA
HENA
WCLKA
WASYN
A
INH
INSU
OUTH
OUTSU
MAX
For dual-module macros, use t
Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from
the DirectTime Analyzer utility.
Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External set-up/hold timing
parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts
(adds) to the internal set-up (hold) time.
V
CC
= 3.0V for 3.3V specifications.
Description
Single Module
Sequential Clk-to-Q
Latch G-to-Q
Flip-Flop (Latch) Reset-to-Q
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
Flip-Flop (Latch) Data Input Set-Up
Flip-Flop (Latch) Data Input Hold
Flip-Flop (Latch) Enable Set-Up
Flip-Flop (Latch) Enable Hold
Flip-Flop (Latch) Clock Active Pulse Width
Flip-Flop (Latch) Asynchronous Pulse Width
Flip-Flop Clock Input Period
Input Buffer Latch Hold
Input Buffer Latch Set-Up
Output Buffer Latch Hold
Output Buffer Latch Set-Up
Flip-Flop (Latch) Clock Frequency
2
1
3, 4
PD1
+ t
RD1
+ t
PDn
, t
CO
Discontinued – v3.0
+ t
Min.
0.4
0.0
0.8
0.0
3.4
3.4
6.8
0.0
0.3
0.0
0.3
‘–3’ Speed
RD1
C C
+ t
= 4 .7 5 V, T
Max.
PDn
215
2.6
2.6
2.6
2.6
1.1
1.3
1.7
2.3
3.4
or t
PD1
Min.
0.4
0.0
0.9
0.0
3.8
3.8
7.7
0.0
0.4
0.0
0.4
‘–2’ Speed
+ t
RD1
J
Max.
190
3.0
3.0
3.0
3.0
1.2
1.4
1.9
2.6
3.8
+ t
= 7 0° C )
SUD
Min.
, whichever is appropriate.
0.5
0.0
1.0
0.0
4.5
4.5
9.1
0.0
0.4
0.0
0.4
‘–1’ Speed
Max.
160
3.5
3.5
3.5
3.5
1.4
1.7
2.2
3.0
4.5
Min.
13.0
0.7
0.0
1.4
0.0
6.4
6.4
0.0
0.6
0.0
0.6
‘Std’ Speed
Max.
110
5.0
5.0
5.0
5.0
2.0
2.4
3.1
4.3
6.4
Min.
10.9
0.6
0.0
1.2
0.0
5.4
5.4
0.0
0.5
0.0
0.5
‘–F’ Speed
Max.
105
4.2
4.2
4.2
4.2
1.7
2.0
2.6
3.6
5.4
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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