CY28312B-2T SPECTRALINEAR [SpectraLinear Inc], CY28312B-2T Datasheet - Page 5

• Manufacturer Part Number: CY28312B-2T
• Manufacturer: SPECTRALINEAR [SpectraLinear Inc]

Rev 1.0, November 21, 2006
Table 3. Byte Read and Byte Write Protocol (continued)
CY28312B-2 Serial Configuration Map
The serial bits will be read by the clock driver in the following
order:
Byte 0–Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1–Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte N–Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 0: Control Register 0
Byte 1: Control Register 1
Byte 2: Control Register 2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit
Bit
Bit
Bit
Byte Write Protocol
42, 41
39, 38
Pin#
Pin#
Pin#
20
18
17
16
14
28
27
26
–
–
–
–
–
–
–
–
6
7
–
Description
PCI7
PCI6
PCI5
PCI4
PCI3
Spread Enable
Spread Select2
Spread Select1
Spread Select0
SEL3
SEL2
SEL1
SEL0
CPUT0, CPUC0
CPUT_CS,
CPUC_CS
48MHz
24_48MHz
Reserved
AGP2
AGP1
AGP0
Name
Name
Name
Default
Default
Default
All unused register bits (reserved and N/A) should be written
to a “0” level.
All register bits labeled “Initialize to 0” must be written to zero
during initialization.
30:37
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
1
1
1
1
1
1
Bit
29
38
39
0 = Disabled
1 = Enabled
‘000’ = ±0.25%
‘001’ = –0.5%
‘010’ = ±0.5%
‘011’ = ±0.38%
‘100’ = Reserved
‘101’ = Reserved
‘110’ = Reserved
‘111’ = Reserved
SW Frequency selection bits. See Table 4.
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Reserved
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Acknowledge from slave
Data byte from slave – 8 bits
Not Acknowledge
Stop
Byte Read Protocol
Description
Description
Description
Description
CY28312B-2
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