CY28312B-2T SPECTRALINEAR [SpectraLinear Inc], CY28312B-2T Datasheet - Page 8

• Manufacturer Part Number: CY28312B-2T
• Manufacturer: SPECTRALINEAR [SpectraLinear Inc]

Rev 1.0, November 21, 2006
Byte 10: Skew Control Register
Byte 11: Recovery Frequency N–Value Register
Byte 12: Recovery Frequency M–Value Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Bit
Bit
ROCV_FREQ_SEL
ROCV_FREQ_M6
ROCV_FREQ_M5
ROCV_FREQ_M4
ROCV_FREQ_M3
ROCV_FREQ_M2
ROCV_FREQ_M1
ROCV_FREQ_M0
ROCV_FREQ_N7
ROCV_FREQ_N6
ROCV_FREQ_N5
ROCV_FREQ_N4
ROCV_FREQ_N3
ROCV_FREQ_N2
ROCV_FREQ_N1
ROCV_FREQ_N0
CPU_Skew2
CPU_Skew1
CPU_Skew0
Reserved
PCI_Skew1
PCI_Skew0
AGP_Skew1
AGP_Skew0
Name
Name
Name
Default
Default
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
If ROCV_FREQ_SEL is set, CY28312B-2 will use the values programmed in
ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] to determine the recovery
CPU output frequency.when a Watchdog timer time-out occurs.
The setting of FS_Override bit determines the frequency ratio for CPU,
SDRAM, AGP and SDRAM. When it is cleared, CY28312B-2 will use the same
frequency ratio stated in the Latched FS[4:0] register. When it is set,
CY28312B-2 will use the frequency ratio stated in the SEL[4:0] register.
CY28312B-2 supports programmable CPU frequency ranging from 50 MHz to
248 MHz.
CY28312B-2 will change the output frequency whenever there is an update to
either ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0]. Therefore, it is recom-
mended to use Word or Block write to update both registers within the same
SMBus bus operation.
ROCV_FREQ_SEL determines the source of the recover frequency when a
Watchdog timer time-out occurs. The clock generator will automatically switch
to the recovery CPU frequency based on the selection on ROCV_FREQ_SEL.
0 = From latched FS[4:0]
1 = From the settings of ROCV_FREQ_N[7:0] & ROCV_FREQ_M[6:0]
If ROCV_FREQ_SEL is set, CY28312B-2 will use the values programmed in
ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] to determine the recovery
CPU output frequency.when a Watchdog timer time-out occurs
The setting of FS_Override bit determines the frequency ratio for CPU,
SDRAM, AGP and SDRAM. When it is cleared, CY28312B-2 will use the same
frequency ratio stated in the Latched FS[4:0] register. When it is set,
CY28312B-2 will use the frequency ratio stated in the SEL[4:0] register.
CY28312B-2 supports programmable CPU frequency ranging from 50 MHz to
248 MHz.
CY28312B-2 will change the output frequency whenever there is an update to
either ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0]. Therefore, it is recom-
mended to use Word or Block write to update both registers within the same
SMBus bus operation.
CPU skew control
000 = Normal
001 = –150 ps
010 = –300 ps
011 = –450 ps
100 = +150 ps
101 = +300 ps
110 = +450 ps
111 = +600 ps
Reserved
PCI skew control
00 = Normal
01 = –500 ps
10 = Reserved
11 = +500 ps
AGP skew control
00 = Normal
01 = –150 ps
10 = +150 ps
11 = +300 ps
Pin Description
Description
Description
CY28312B-2
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