CY28405OC-2 SPECTRALINEAR [SpectraLinear Inc], CY28405OC-2 Datasheet - Page 20

• Manufacturer Part Number: CY28405OC-2
• Description: Clock Synthesizer with Differential SRC and CPU Outputs
• Manufacturer: SPECTRALINEAR [SpectraLinear Inc]

Rev 1.0, November 22, 2006
Table 4. Block Read and Block Write Protocol (continued)
Table 5. Byte Read and Byte Write Protocol
Byte Configuration Map
Byte 0: Control Register
11:18
20:27
Bit
Bit
Bit
2:8
....
....
....
....
....
10
19
28
29
4
3
2
1
0
1
9
7
6
5
Data Byte (N–1) –8 bits
Acknowledge from slave
Data Byte N –8 bits
Acknowledge from slave
Stop
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
'100xxxxx' stands for byte operation, bits[6:0] of the
command code represents the offset of the byte to
be accessed
Acknowledge from slave
Data byte from master – 8 bits
Acknowledge from slave
Stop
@Pup
HW
HW
0
1
0
0
1
1
Block Write Protocol
Byte Write Protocol
Reserved
PCIF
PCI
Reserved
Reserved
Reserved
Reserved
FS_B
FS_A
Description
Description
Name
Reserved, set = 0
Reserved, set = 1
Reserved, set = 1
Reserved, set = 0
PCI Drive Strength Override
0 = Force All PCI and PCIF Outputs to Low Drive Strength
1 = Force All PCI and PCIF Outputs to High Drive Strength
Reserved, set = 0
Power-up latched value of FS_B pin
Power-up latched value of FS_A pin
48:55
21:27
30:37
11:18
Bit
47
56
....
....
....
Bit
2:8
10
19
20
28
29
38
39
1
9
Acknowledge from master
Data byte from slave – 8 bits
Acknowledge from master
Data byte N from slave – 8 bits
Acknowledge from master
Stop
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
'100xxxxx' stands for byte operation, bits[6:0] of
the command code represents the offset of the
byte to be accessed
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read = 1
Acknowledge from slave
Data byte from slave – 8 bits
Acknowledge from master
Stop
Description
Block Read Protocol
Byte Read Protocol
Description
Description
CY28405-2
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