CY28405OC-2 SPECTRALINEAR [SpectraLinear Inc], CY28405OC-2 Datasheet - Page 24

• Manufacturer Part Number: CY28405OC-2
• Description: Clock Synthesizer with Differential SRC and CPU Outputs
• Manufacturer: SPECTRALINEAR [SpectraLinear Inc]

Rev 1.0, November 22, 2006
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
CL ................................................... Crystal load capacitance
CLe .........................................Actual loading seen by crystal
Ce .....................................................External trim capacitors
Cs .............................................Stray capacitance (trace,etc)
Ci .............Internal capacitance (lead frame, bond wires etc)
PD# (Power-down) Clarification
The PD# (Power Down) pin is used to shut off ALL clocks prior
to shutting off power to the device. PD# is an asynchronous
active LOW input. This signal is synchronized internally to the
device powering down the clock synthesizer. PD# is an
asynchronous function for powering up the system. When PD#
......................................using standard value trim capacitors
Cs1
Figure 2. Crystal Loading Example
Ce1
Load Capacitance (each side)
X1
Ci1
Ce = 2 * CL – (Cs + Ci)
(CY28405-2)
Clock Chip
XTAL
Ci2
X2
Ce2
Cs2
3 to 6p
33pF
Trim
Pin
Trace
2.8pF
CLe
As mentioned previously, the capacitance on each side of the
crystal is in series with the crystal. This mean the total capac-
itance on each side of the crystal must be twice the specified
load capacitance (CL). While the capacitance on each side of
the crystal is in series with the crystal, trim capac-
itors(Ce1,Ce2) should be calculated to provide equal capaci-
tative loading on both sides.
Use the following formulas to calculate the trim capacitor
values fro Ce1 and Ce2.
is low, all clocks are driven to a LOW value and held there and
the VCO and PLLs are also powered down. All clocks are shut
down in a synchronous manner so has not to cause glitches
while transitioning to the low ‘stopped’ state.
PD# – Assertion
When PD# is sampled low by two consecutive rising edges of
CPUC clock then all clock outputs (except CPU) clocks must
be held low on their next high to low transition. CPU clocks
must be hold with CPU clock pin driven high with a value of 2x
Iref and CPUC undriven.
Due to the state of internal logic, stopping and holding the REF
clock outputs in the LOW state may require more than one
clock cycle to complete.
Total Capacitance (as seen by the crystal)
=
(
Ce1 + Cs1 + Ci1
1
+
1
Ce2 + Cs2 + Ci2
1
CY28405-2
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