MG84FL54BD MEGAWIN [Megawin Technology Co., Ltd], MG84FL54BD Datasheet
MG84FL54BD
Related parts for MG84FL54BD
MG84FL54BD Summary of contents
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General Description ..........................................................................................................4 2. Features ........................................................................................................................... 5 3. Block Diagram ..................................................................................................................6 4. Pin Configurations ............................................................................................................7 4.1. Pin-out for 48-pin Package ......................................................................................7 4.2. Pin Description.........................................................................................................8 5. Special Function Registers (SFRs)................................................................................. 10 5.1. SFR Mapping.........................................................................................................10 5.2. The Standard 8051 SFRs ...................................................................................... ...
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Keypad Interrupt .............................................................................................................40 15. Wake-up from Power-down Mode ..................................................................................41 15.1. Power-down Wake-up Sources ............................................................................. 41 15.2. Sample Code for Wake-up from Power-down........................................................ 42 16. Serial Peripheral Interface (SPI) ..................................................................................... 43 16.1. Typical SPI Configurations .................................................................................... 45 16.1.1. Single Master ...
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Hardware Option.............................................................................................................83 25. Instruction Set................................................................................................................. 85 25.1. Arithmetic Operations ............................................................................................86 25.2. Logic Operations.................................................................................................... 87 25.3. Data Transfer.........................................................................................................88 25.4. Boolean Variable Manipulation .............................................................................. 89 25.5. Program and Machine Control ...............................................................................90 26. Absolute Maximum Rating..............................................................................................91 27. Electrical Characteristics ................................................................................................91 27.1. Global ...
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General Description MG84FL54B is an enhanced single-chip 8-bit microcontroller manufactured in an advanced Embedded-Flash process. The instruction set is fully compatible with that of the 8051. With the enhanced CPU core, the device needs only clock ...
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Features 1-T 8051 CPU Core 16K bytes of on-chip Flash program memory with ISP/IAP function 256 bytes internal scratch-pad RAM and 576 bytes on-chip expanded RAM (XRAM) Dual DPTR (Data Pointer register) Four and half configurable I/O ports Three ...
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Block Diagram DP, DM USB Control RST RESET Logic XIN PLL WDT XOUT Port4 Latch Port3 Latch Port4 Driver Port3 Driver P4.0 ~ P4.3 P3.0 ~ P3.7 6 XRAM576 1-T 8051 RAM256 CPU Core Port2 Latch Port1 Latch Port2 ...
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... VDDA VSSA 4 P43 5 P42 6 P41 7 VDD_PLL 8 PLL_CV 9 RXD/P30 10 TXD/P31 11 INT0/P32 MEGAWIN MG84FL54BD 31 LQFP48 MG84FL54B Data sheet RST P05/KBI5 P04/KBI4 P03/KBI3 P02/KBI2 P01/KBI1 P00/KBI0 P17 P16 P15 P14 P13 7 ...
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Pin Description Pin No. Name Type 1 VDDA I/O 4 VSSA 5 P4.3 I/O 6 P4.2 I/O 7 P4.1 I/O 8 VDD_PLL 9 PLL_CV I/O P3.0 10 I/O /RXD P3.1 11 I/O /TXD P3.2 ...
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P0.4 I/O 35 P0.5 I/O 36 RST 37 P0.6 I/O 38 P0.7 I/O P2.0 39 I/O /TWSI_SCL P2.1 40 I/O /TWSI_SDA 41 P4.0 I/O 42 VSS P 43 XOUT O 44 XIN P2.4 45 I/O /SPI_SSI P2.5 46 I/O ...
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Special Function Registers (SFRs) 5.1. SFR Mapping 0/8 1/9 SICON F8H F0H B E8H P4 E0H ACC WDTCR D8H D0H PSW SIADR C8H T2CON T2MOD C0H XICON B8H IP SADEN B0H P3 P3M0 IE SADDR A8H P2 A0H SCON ...
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The Standard 8051 SFRs SYMBOL DESCRIPTION ADDR * Accumulator ACC * B Register B * Program Status Word PSW SP Stack Pointer DPH Data Pointer High DPL Data Pointer Low * Port Port ...
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The Auxiliary SFRs SYMBOL DESCRIPTION ADDR Interrupt External Interrupt * XICON Control Auxiliary AUXIE Interrupt Enable Auxiliary AUXIP Interrupt Priority I/O Port * Port 4 P4 P0M0 Port 0 Mode Register 0 P0M1 Port 0 Mode Register 1 P1M0 ...
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ISP Flash Address IFADRH High IFADRL ISP Flash Address Low IFD ISP Flash Data ISP Sequential SCMD Command Notes: *: bit addressable -: reserved bit MEGAWIN E3H E4H E2H E6H MG84FL54B Data sheet 00H 00H FFH xxH 13 ...
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Flash Memory Configuration There are total 16K bytes of Flash Memory. Note: In default, the samples that Megawin released had configured the flash memory for 2K ISP, 1K IAP and Lock enabled. The 2K ISP region is inserted Megawin ...
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On-chip expanded RAM (XRAM) In addition to the 256 bytes of scratch-pad RAM, there are extra 576 bytes of on-chip expanded RAM (XRAM) . They may be accessed by the instructions “MOVX @Ri” and “MOVX @DPTR”. Using the XRAM ...
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Dual Data Pointer Register (DPTR) The dual DPTR structure (see the following Figure way by which the chip can specify the address of an external data memory location. There are two 16-bit DPTR registers that address the ...
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Configurable I/O Ports 9.1. Port Configurations The device has five I/O ports, Port 0 ~ Port 4. All the port pins can be individually and independently configured to one of four modes: quasi-bidirectional (standard 8051 I/O port), push-pull output, ...
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P4M0 (Address=B3H, Port 4 Mode Register P4M1 (Address=B4H, Port 4 Mode Register 9.1.1. Quasi-bidirectional Port pins in quasi-bidirectional mode are similar to the standard 8051 port pins. A quasi-bidirectional port can be ...
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Input-Only (Hi-Z) The input-only configuration is a Schmitt-triggered input without any pull-up resistors on the pin. MEGAWIN MG84FL54B Data sheet 19 ...
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Push-Pull Output The push-pull output configuration has the same pull-down structure as both the open-drain and the quasi- bidirectional output modes, but provides a continuous strong pull-up when the port register contains a logic “1”. The push-pull mode may ...
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Three 16-bit Timers 10.1. Timer 0 and Timer 1 After power-up or reset, the default function and operation of Timer 0 and Timer 1 is fully compatible with the standard 8051 MCU. The only difference is that besides Fosc/12 ...
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Mode 1: 16-bit Counter Where OSC means Fosc, the system clock. 10.1.3. Mode 2: 8-bit Auto-reload Where OSC means Fosc, the system clock. 22 MG84FL54B Data Sheet MEGAWIN ...
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Mode 3: Timer 0 as Two 8-bit Counter Where OSC means Fosc, the system clock. 10.1.5. Programmable Clock Output from Timer 0 The user can get a 50% duty-cycle clock output on P3.4 by configuring Timer 0 as 8-bit ...
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Timer 2 Three special function registers, AUXR, T2MOD and T2CON, are related to the operation of Timer 2, as listed below. AUXR (Address=8EH, Auxiliary Register BRADJ0 T2X12: Timer 2 clock source select while C/T2 ...
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After reset, the DCEN=0 (T2MOD.0), which makes the function of Timer 2 all the same as the standard 8052 (always counts up). While DCEN=1, Timer 2 can count up or count down according to the logic level of the T2EX ...
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Auto-Reload Mode (AR mode, Timer2 can be configured to count up or count down depending on DCEN bit in T2MOD register. When reset is applied(DCEN =0, CP/RL2=0), Timer2 is at auto-reload mode and only counting up is ...
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When DCEN =1 and in AR mode, Timer2 can be configured to count up or down . The counting direction is determined by T2EX pin. If T2EX=1, counting up, otherwise counting down. An overflow on Timer2 will set TF2 and ...
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Baud-Rate Generator Mode (BRG) Timer2 can be configured to generate various baud-rate. TCLK and/or RCLK in T2CON allow the serial port transmit and receive baud rates to be derived from either Timer1 or Timer2. When TCLK=0, Timer1 or S2BRT ...
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Programmable Clock Output from Timer 2 Timer 2 has a Clock-Out Mode (while CP/-RL2=0 & T2OE=1). In this mode, Timer 2 operates as a programmable clock generator with 50% duty-cycle. The generated clocks come out on P1.0. The input ...
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Enhanced UART 11.1. Frame Error Detection While the SMOD0 bit (in PCON, bit 6) is set, the hardware will set the FE bit (SCON.7) when an invalid stop bit is detected. The FE bit is not cleared by valid ...
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Broadcast address. Two special Function Registers are used to define the slave’s address, SADDR, and the address mask, SADEN. SADEN is used to define which bits in the SADDR are to be used and which bits are “don’t care”. The ...
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Baud Rate Setting All the four operation modes of the serial port are the same as those of the standard 8051 except the baud rate setting. Three registers, PCON, AUXR and AUXR2, are related to the baud rate setting: ...
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Baud Rate in Mode 2 BRADJ = 0 SMOD 2 B. (The same as standard 8051) Baud Rate in Mode 1 & 3 (1) Using Timer 1 as the Baud Rate Generator SMOD 2 B.R. = T1X12 = ...
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Using Timer 2 as the Baud Rate Generator When Timer 2 is used as the baud rate generator (either TCLK or RCLK in T2CON is ‘1’), the baud rate is as follows. BRADJ = 0 Fosc x B.R. = ...
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Interrupt The device has a total of 12 interrupt sources. Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt Enable registers (IE, AUXIE and XICON). And, each interrupt ...
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AUXIE (Address=ADH, Interrupt Enable Register EUSB ETWSI EKBI EUSB: USB interrupt enable bit. ETWSI: 2-wire-Serial-Interface interrupt enable bit. EKBI: Keypad interrupt enable bit. ESPI: SPI interrupt enable bit. XICON (Address=C0H, External Interrupt Control Register ...
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PKBI: Keypad interrupt priority bit. PSPI: SPI interrupt priority bit. 12.1. Two Priority Levels The bit values in the register IP and AUXIP determine what priority level each interrupt has. The following tables show the bit values and priority levels ...
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Interrupt System /INT0 TF0 /INT1 TF1 RI TI TF2 INT2 INT3 SPIF KBIF SI USB Individual Enable 12.3. Note on Interrupt during ISP/IAP During ISP/IAP, the CPU halts for a while for internal ISP/IAP processing. At this time, the ...
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Additional External Interrupts (INT2 and INT3) The device has two additional external interrupt inputs: INT2 (P3.6) and INT3 (P3.7). They are identical to /INT0 (P3.2) or /INT1 (P3.3) except the edge-triggered type (ITx=1) can be programmed to be rising-edge ...
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Keypad Interrupt The Keypad Interrupt function is intended primarily to allow a single interrupt to be generated when Port 1 is equal to or not equal to a certain pattern. This function can be used for bus address recognition ...
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Wake-up from Power-down Mode When the CPU is put into power-down mode, the external interrupts (/INT0, /INT1, INT2 and INT3), keypad interrupt and USB interrupt will wake up the CPU if any of them is enabled. 15.1. Power-down Wake-up ...
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Sample Code for Wake-up from Power-down Note: /INT0 is used in this example. ;****************************************************************************************** ; Wake-up-from-power-down by /INT0 interrupt ;****************************************************************************************** INT0 BIT 0B2H EA BIT 0AFH EX0 BIT 0A8H CSEG AT 0000h JMP start ; CSEG AT 0003h JMP ...
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Serial Peripheral Interface (SPI) The device provides a high-speed serial communication interface, the SPI interface. SPI is a full-duplex, high- speed and synchronous communication bus with two operation modes: Master mode and Slave mode Mbps can ...
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SSIG: /SS is ignored If SSIG=1, MSTR decides whether the device is a master or slave. If SSIG=0, the /SS pin decides whether the device is a master or slave. SPEN: SPI enable If SPEN=1, the SPI is enabled. If ...
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Typical SPI Configurations 16.1.1. Single Master & Single Slave For the master: can use any port pin, including P2.4 (/SS), to drive the /SS pin of the slave. For the slave: SSIG is ‘0’, and /SS pin is used ...
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Single Master & Multiple Slaves For the master: can use any port pin, including P2.4 (/SS) to drive the /SS pins of the slaves. For all the slaves: SSIG is ‘0’, and are selected by their corresponding /SS pins. ...
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Configuring the SPI Table: SPI Master and Slave Selection SPEN SSIG /SS (SPCTL. (SPCTL. (SPCTL. -pin ...
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Mode Change on /SS-pin If SPEN=1, SSIG=0, MSTR=1 and /SS pin=1, the SPI is enabled in master mode. In this case, another master can drive this pin low to select this device as an SPI slave and start sending ...
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Data Mode Clock Phase Bit (CPHA) allows the user to set the edges for sampling and changing data. The Clock Polarity bit, CPOL, allows the user to set the clock polarity. The following figures show the different settings of ...
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SPI Master Transfer Format with CPHA=0 16.3.4. SPI Master Transfer Format with CPHA=1 50 MG84FL54B Data Sheet MEGAWIN ...
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Serial Interface (TWSI) Features • Simple yet powerful and flexible communication interface, only two bus lines needed. • Both Master and Slave operation supported, and device can operate as Transmitter or Receiver. • 7-bit address space allows up ...
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The Special Function Registers for TWSI The Serial Interface Address Register, SIADR, Address=D1H The CPU can read from and write to this register directly. SIADR is not affected by the TWSI hardware. The contents of this register are irrelevant ...
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STA, the START Flag When the STA bit is set to enter a master mode, the TWSI hardware checks the status of the serial bus and generates a START condition if the bus is free. If the bus is not ...
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Table: Serial Clock Rates CR2 CR1 CR0 Where, Fosc is the system clock. The Status Register, ...
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START condition is transmitted, the serial interrupt flag (SI) is set, and the status code in the status register (SISTA) will be 08H. This status code must be used to vector to an interrupt service routine that loads SIDAT with ...
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However, the serial bus is still monitored, and address recognition may be resumed at any time by setting AA. This means that the AA bit may be used to temporarily isolate TWSI from ...
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Miscellaneous States There are two SISTA codes that do not correspond to a defined TWSI hardware state, as described below. S1STA = F8H: This status code indicates that no relevant information is available because the serial interrupt flag, SI, ...
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Using the TWSI The TWSI is byte-oriented and interrupt based. Interrupts are issued after all bus events, like reception of a byte or transmission of a START condition. Because the TWSI is interrupt-based, the application software is free to ...
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Master/Transmitter Mode From Slave Mode (STA,STO,SI,AA)=(0,0,0,X) Data byte will be transmitted; ACK will be received. 28H Data byte in SIDAT has been transmitted; ACK has been received. or 30H Data byte in SIDAT has been transmitted; NOT ACK has ...
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Master/Receiver Mode From Master/Transmitter 48H SLA+R has been transmitted; NOT ACK has been received. (STA,STO,SI,AA)=(1,1,0,X) A STOP followed by a START will be transmitted; STO flag will be reset. Send a STOP followed by a START 38H Arbitration lost ...
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Slave/Transmitter Mode (STA,STO,SI,AA)=(0,0,0,0) Last data byte will be transmitted; ACK will be received. C8H Last data byte in SIDAT has been transmitted; ACK has been received. (STA,STO,SI,AA)=(1,0,0,1) (STA,STO,SI,AA)=(1,0,0,0) Switch to not addressed SLV mode; Switch to not addressed SLV ...
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Slave/Receiver Mode (STA,STO,SI,AA)=(0,0,0,0) Data byte will be received; NOT ACK will be returned. 88H Data byte has been received; NOT ACK has been returned. A0H A STOP or repeated START has been received while still addressed as SLV/REC. (STA,STO,SI,AA)=(1,0,0,1) ...
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Slave/Receiver Mode (For General Call) (STA,STO,SI,AA)=(0,0,0,0) Data byte will be received; NOT ACK will be returned. 98H Previously addressed with General Call address; Data byte has been received; NOT ACK has been returned. A0H A STOP or repeated START ...
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One-Time-Enabled Watchdog Timer (WDT) The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 15-bits free-running counter, an 8-bit prescaler and a control register (WDTCR). ...
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PS2 PS1 PS0 Prescaler value 128 256 18.2. WDT During ...
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PS2 PS1 PS0 Prescaler value 128 256 18.5. Sample Code for WDT Condition: Fosc=6MHz Target: WDT ...
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Universal Serial Bus (USB) 19.1. USB Block Diagram DP USB Transceiver DM 256 Bytes FIFO 19.2. USB FIFO Management MEGAWIN USB Core 1T 8051 Core USB SFR MOVX MG84FL54B Data sheet 67 ...
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USB Special Function Registers To activate the USB operation, the user should enable PLL (by setting bit ‘EN_PLL’) and enable USB function (by setting bit ‘EN_USB’). Clearing bit ‘EN_USB’ will deactivate the USB operation and let the USB function ...
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USB SFR Description “MOVX” SYMBOL DESCRIPTION ADDR Bit-7 Device Control DCON C0H Register USB Address UADDR D8H Register USB Power UPCON C9H Control Register Interrupt Enable IEN D9H Register USB Interrupt UIE DAH Enable Register USB Interrupt UIFLG DBH ...
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DCON (Device Control Register, Address=C0H, SYS_reset=xxxx-0xxx, Read/Write Bit7~4: Reserved, always write 0. Bit3: EP3DIR-- USB Endpoint 3 Direction select. When this bit is set to “1”, EP3 will behave endpoint. When ...
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Bit2: EFSR-- Enable USB Function’s Suspend/Resume interrupt. If this bit is set, enables function’s interrupt of UPCON events. Function suspend/resume/remote- wakeup/USB-reset interrupt enable bit. This bit doesn't be reset USB_RESET. Default is cleared. Bit1: EF-- Enable USB Function’s interrupt Flag. ...
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Bit1: URXD0-- USB Receive Done Flag for endpoint 0. This bit is set by hardware when detected a receive done on endpoint 0. uC can read/write-clear on this bit. This bit is cleared when firmware writes '1' to it. Bit0: ...
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Bit4: TXDBM-- Transmit Endpoint Dual Buffer Mode. Set this bit to enable the dual buffer transfer for IN transaction. Default is cleared. This bit is only valid for endpoint 2. Bit3: RXISO-- Receive Isochronous Type Enable. Set this bit to ...
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Receive FIFO data specified by EPINDEX is stored and read from this register. RXCON (Receive FIFO Control Register, Endpoint-Indexed, Address=E4H, SYS/USB_reset=0xxx-0xxx, Write- only RXCLR - - Bit7: RXCLR-- Receive FIFO Clear. Set this bit to flush the ...
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Set this bit to flush the entire transmit FIFO. All FIFO statuses are reverted to their reset states. Hardware clears this bit when the flush operation is completed. Bit6~5: Reserved. Bit4: TXFFRC-- Transmit FIFO Write Complete. Set this bit to ...
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In-System-Programming (ISP) The Flash program memory supports both parallel programming and serial In-System Programming (ISP). Parallel programming mode offers high-speed programming. ISP allows a device to be reprogrammed in the end product under software control. The capability to field ...
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Description for ISP Operation Before doing ISP operation, the user should fill the bits XCKS4~XCKS0 in CKCON register with a proper value. (Refer to Section “System Clock”.) To do Page Erase (64 Bytes per Page) Step1: Set [MS1,MS0]=[1,1] in ...
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Demo Program for ISP ;****************************************************************************************** ; Demo Program for the ISP ;****************************************************************************************** IFD DATA 0E2h IFADRH DATA 0E3h IFADRL DATA 0E4h ISPTME DATA 0E5h SCMD DATA 0E6h ISPCR DATA 0E7h ; MOV ISPCR,#10000000b ;============================================================================= ; 1. Page Erase Mode ...
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In-Application-Programming (IAP) The device is In Application Programmable (IAP), which allows some region in the Flash memory to be used as non-volatile data storage while the application program is running. This useful feature can be applied to the application ...
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System Clock 22.1. Programmable System Clock The system clock (or CPU clock) of the device is programmable and source-selectable. The user can program the system clock frequency by bits CKS2~CKS0 (CKCON.2 ~ CKCON.0) and select the clock source by ...
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CKCON2 (Address=BFH, Clock Control Register OSCDR0 OSCDR0: On-chip XTAL oscillating driving control bits. 0 select the maximum driving, and 1 selects the minimum driving. EN_PLL: PLL enable bit. 1: Enable; 0: Disable PLL_RDY: It ...
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Power-On Reset The CPU will not start to work until the VCC power rises up to the Power-On Reset (POR) voltage. It means the POR state is activated whenever the VCC level is below the POR voltage. The Power-On ...
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Hardware Option The device has the variety of hardware options, which can only be programmed through a universal Writer/Programmer. OR0 (Option Register ISP_S2 ISP_S1 ISP_S0 HWBS: 0 (enabled): When power-up, MCU will boot from ISP-memory ...
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PSMEN: 0 (enabled): Power saving mode enable 1 (disable): Power saving mode disable OR3 (Option Register WDTCR_WP - HWENW WDTCR_WP: 0 (enabled): If CPU runs in AP-memory, the register WDTCR ...
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Instruction Set The Instruction Set is fully compatible with that of the standard 8051 except the execution time, i.e., the number of clock cycles required to execute an instruction. The shortest execution time is just one system clock cycle ...
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Arithmetic Operations Mnemonic Description ARITHMETIC OPERATIONS ADD A,Rn Add register to ACC ADD A,direct Add direct byte to ACC ADD A,@Ri Add indirect RAM to ACC Add immediate data to ACC ADD A,#data ADDC A,Rn Add register to ACC ...
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Logic Operations Mnemonic Description LOGIC OPERATIONS ANL A,Rn AND register to ACC ANL A,direct AND direct byte to ACC ANL A,@Ri AND indirect RAM to ACC ANL A,#data AND immediate data to ACC ANL direct,A AND ACC to direct ...
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Data Transfer Mnemonic Description DATA TRANSFER MOV A,Rn Move register to ACC MOV A,direct Move direct byte o ACC MOV A,@Ri Move indirect RAM to ACC MOV A,#data Move immediate data to ACC MOV Rn,A Move ACC to register ...
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Boolean Variable Manipulation Mnemonic Description BOOLEAN VARIABLE MANIPULATION CLR C Clear Carry CLR bit Clear direct bit Set Carry SETB C SETB bit Set direct bit CPL C Complement Carry CPL bit Complement direct bit ANL C,bit AND direct ...
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Program and Machine Control Mnemonic Description PROAGRAM AND MACHINE CONTROL ACALL addr11 Absolute subroutine call LCALL addr16 Long subroutine call RET Return from subroutine RETI Return from interrupt subroutine AJMP addr11 Absolute jump LJMP addr16 Long jump SJMP rel ...
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Absolute Maximum Rating Parameter Ambient temperature under bias Storage temperature Voltage on any GPIO pin or RST with respect to Ground Voltage on DP，DM and PLL_CV with respect to Ground Voltage on VDD_IO with respect to Ground Voltage on ...
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USB Transceiver Electrical Characteristics VSS = 0V ℃ , VDD_IO= 2.4V~5.5V, VDD_CORE= VDDA= VDD_PLL= 3.3V, unless otherwise specified Symbol Parameter Transmitter V Output High Voltage OH V Output Low Voltage OL V Output Cross Over point ...
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... Field Applications Home Appliance Healthcare POS Control Wireless Dongle Joy Stick Wireless Keyboard/Mouse 29. Order Information Part Number MG84FL54BD 30. Package Dimension MG84FL54BD (LQFP-48) MEGAWIN Temperature Range Package -40℃~85℃ LQFP-48 MG84FL54B Data sheet Packing Operation Voltage Tray 3.3V 93 ...
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Revision History Version Date V0.96 2007/11 2007/12 P95,96 V0.97 2008/01 P7 V0.98 A1 2008/06 A2 2008/12 94 Page Description - Initial public data sheet. - Add maximum rating and Electrical Characteristics. - Extend flash data retention from 7 to ...