MG84FL54BD MEGAWIN [Megawin Technology Co., Ltd], MG84FL54BD Datasheet - Page 76

• Manufacturer Part Number: MG84FL54BD
• Description: Full-Speed USB micro-controller
• Manufacturer: MEGAWIN [Megawin Technology Co., Ltd]

20. In-System-Programming (ISP)
The Flash program memory supports both parallel programming and serial In-System Programming (ISP).
Parallel programming mode offers high-speed programming. ISP allows a device to be reprogrammed in the
end product under software control. The capability to field update the application firmware makes a wide range
of applications possible.
Prior to using the ISP feature, the user should configure an ISP-memory by a universal Writer or Programmer.
Refer to Section “Hardware Option” for the ISP-memory configuration.
The following special function registers are related to ISP:
ISPCR: Address=E7H, ISP Control Register
IFADRH: Address=E3H, ISP Flash Address High Register
IFADRL: Address=E4H, ISP Flash Address Low Register
IFD: Address=E2H, ISP Flash Data Register
SCMD: Address=E6H, ISP Sequential Command Register.
ISPCR (Address=E7H, ISP Control Register)
Note: The reset value is #00000000B.
Bit7: ISPEN: Set to enable ISP function.
Bit6: SWBS:
Bit5: SWRST: Write ‘1’ to trigger software reset.
Bit4: Reserved
Bit3: MISPF, Megawin proprietary ISP Flag. If use Megawin proprietary ISP code on USB DFU from AP region,
Bit2: Reserved.
Bit1~0: MS1~MS0, ISP mode select, as listed below.
76
ISPEN
MS1
7
Software boot select. Set to select booting from ISP-memory, and clear to select booting from AP-memory
after software reset.
cpu must write 1 to SWRST and MISPF concurently to trigger the ISP routine. If user only set a soft reset
or perform IAP flow, must write “0” on this bit.
0
0
1
1
MS0
0
1
0
1
SWBS
6
SWRST
Byte Program
5
Page Erase
ISP Mode
Standby
Read
Reserved
MG84FL54B Data Sheet
4
MISPF
3
Reserved
2
MS1
1
MS0
0
MEGAWIN