PF38F5070M0Y0T0 NUMONYX [Numonyx B.V], PF38F5070M0Y0T0 Datasheet - Page 36

• Manufacturer Part Number: PF38F5070M0Y0T0
• Description: Numonyx StrataFlash Wireless Memory
• Manufacturer: NUMONYX [Numonyx B.V]

9.0
9.1
9.1.1
9.1.2
Note:
9.1.3
Datasheet
36
Device Operations
This section provides an overview of device operations. The system CPU provides
control of all in-system read, write, and erase operations of the device via the system
bus. The on-chip Write State Machine (WSM) manages all block-erase and word-
program algorithms.
Device commands are written to the Command User Interface (CUI) to control all flash
memory device operations. The CUI does not occupy an addressable memory location;
it is the mechanism through which the flash device is controlled.
Bus Operations
CE#-low and RST# high enable device read operations. The device internally decodes
upper address inputs to determine the accessed partition. ADV#-low opens the internal
address latches. OE#-low activates the outputs and gates selected data onto the I/O
bus.
In asynchronous mode, the address is latched when ADV# goes high. In synchronous
mode, the address is latched by the first of either the rising ADV# edge or the next
valid CLK edge with ADV# low (WE# and RST# must be VIH; CE# must be VIL).
Reads
To perform a read operation, RST# and WE# must be deasserted while CE# and OE#
are asserted. CE# is the device-select control. When asserted, it enables the flash
memory device. OE# is the data-output control. When asserted, the addressed flash
memory data is driven onto the I/O bus. See
page 41
States” on page 66
The Automatic Power Savings (APS) feature provides low power operation following
reads during active mode. After data is read from the memory array and the address
lines are quiescent, APS automatically places the device into standby. In APS, device
current is reduced to I
Writes
To perform a write operation, both CE# and WE# are asserted while RST# and OE# are
deasserted. All device write operations are asynchronous, with CLK being ignored.
During a write operation, address and data are latched on the rising edge of WE# or
CE#, whichever occurs first.
bus cycle sequence for each of the supported device commands, while
“Command Codes and Definitions” on page 39
7.0, “AC Characteristics” on page 20
Write operations with invalid V
should not be attempted.
Output Disable
When OE# is deasserted, device outputs AD[15:0] are disabled and placed in a high-
impedance (High-Z) state.
for details on the available read modes, and see
for details regarding the available read states.
CCAPS
(see
Table 17, “Command Bus Cycles” on page 38
CC
Section 6.1, “DC Current Characteristics” on page
and/or V
for signal-timing details.
Numonyx™ StrataFlash
PP
voltages can produce spurious results and
Section 10.0, “Read Operations” on
describes each command. See
Section 15.0, “Special Read
®
Wireless Memory (L18 AD-Mux)
Order Number: 313295-04
Table 18,
shows the
November 2007
Section
18).