PF38F5070M0Y0T0 NUMONYX [Numonyx B.V], PF38F5070M0Y0T0 Datasheet - Page 46

• Manufacturer Part Number: PF38F5070M0Y0T0
• Description: Numonyx StrataFlash Wireless Memory
• Manufacturer: NUMONYX [Numonyx B.V]

Note:
10.3.4
Figure 18: Data Hold Timing
10.3.5
Datasheet
46
Data Hold
Data Hold
1 CLK
2 CLK
Active: WAIT is asserted until data becomes valid, then de-asserts. WAIT is asserted during the initial access (latency) and
at the end of the burst cycle with OE# low.
Data Hold
For burst read operations, the Data Hold (DH) bit determines whether the data output
remains valid on AD[15:0] for one or two clock cycles. This period of time is called the
“data cycle”. When DH is set, output data is held for two clocks (default). When DH is
cleared, output data is held for one clock (see
time and the flash memory’s clock-to-data output delay should be considered when
determining whether to hold output data for one or two clocks.
A method for determining the Data Hold configuration is shown below:
To set the device at one clock data hold for subsequent reads, the following condition
must be satisfied:
For example, with a clock frequency of 54 MHz, the clock period is 18.5 ns. Assuming
t
The equation is satisfied and data will be available at every clock period with data hold
setting at one clock.
If t
must be used.
WAIT Delay
The WAIT Delay (WD) bit controls the WAIT assertion-delay behavior during
synchronous burst reads. WAIT can be asserted either during or one data cycle before
valid data is output on AD[15:0]. When WD is set, WAIT is de-asserted one data cycle
before valid data (default). When WD is cleared, WAIT is de-asserted during valid data.
CHQV
CHQV (ns) +
AD[15:0] [Q]
AD[15:0] [Q]
= 14ns and t
t
t
CLK [C]
14 ns + 4 ns
CHQV (ns) +
DATA
= Data set up to Clock (defined by CPU)
t
DATA
DATA
(ns) > One CLK Period (ns), data hold setting of 2 clock periods
t
DATA
≤
18.5 ns
= 4ns. Applying these values to the formula above:
(ns)
≤
One CLK Period (ns)
Output
Valid
Numonyx™ StrataFlash
Output
Valid
Figure
Output
Valid
18). The processor’s data setup
®
Wireless Memory (L18 AD-Mux)
Output
Order Number: 313295-04
Valid
Output
Valid
November 2007