S29GL-P_12 SPANSION [SPANSION], S29GL-P_12 Datasheet - Page 11
S29GL-P_12
Manufacturer Part Number
S29GL-P_12
Description
1 Gigabit, 512 Megabit, 256 Megabit and 128 Megabit 3.0 Volt-only Page Mode Flash Memory featuring 90 nm MirrorBit Process Technology
Manufacturer
SPANSION [SPANSION]
Datasheet
1.S29GL-P_12.pdf
(81 pages)
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2. Input/Output Descriptions & Logic Symbol
October 22, 2012 S29GL-P_00_A14
Table 2.1
DQ14–DQ0
WP#/ACC
DQ15/A-1
RESET#
Symbol
A25–A0
RY/BY#
BYTE#
WE#
OE#
CE#
V
V
V
NC
CC
SS
IO
identifies the input and output package connections provided on the device.
No Connect
Supply
Supply
Supply
Output
Type
Input
Input
Input
Input
Input
Input
Input
I/O
I/O
D a t a
Address lines for GL01GP
A24–A0 for GL512P
A23–A0 for GL256P,
A22–A0 for GL128P.
Data input/output.
DQ15: Data input/output in word mode.
A-1: LSB address input in byte mode.
Chip Enable.
Output Enable.
Write Enable.
Device Power Supply.
Versatile IO Input.
Ground.
Not connected internally.
Ready/Busy. Indicates whether an Embedded Algorithm is in progress or complete. At
V
Selects data bus width. At VIL, the device is in byte configuration and data I/O pins DQ0-
DQ7 are active and DQ15/A-1 becomes the LSB address input. At VIH, the device is in
word configuration and data I/O pins DQ0-DQ15 are active.
Hardware Reset. Low = device resets and returns to reading array data.
Write Protect/Acceleration Input. At V
outermost sectors. At V
unlock bypass mode. Should be at V
up; when unconnected, WP# is at V
S29GL-P MirrorBit
IL
, the device is actively erasing or programming. At High Z, the device is in ready.
S h e e t
Table 2.1 Input/Output Descriptions
®
Flash Family
HH
, accelerates programming; automatically places device in
IH
IH
IL
.
Description
, disables program and erase functions in the
for all other conditions. WP# has an internal pull-
11
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