S29GL-P_12 SPANSION [SPANSION], S29GL-P_12 Datasheet - Page 77

• Manufacturer Part Number: S29GL-P_12
• Description: 1 Gigabit, 512 Megabit, 256 Megabit and 128 Megabit 3.0 Volt-only Page Mode Flash Memory featuring 90 nm MirrorBit Process Technology
• Manufacturer: SPANSION [SPANSION]

D a t a
S h e e t
Figure 13.2 Warm Reset Timing
Note:
The sum of t
and t
must be equal to or greater than t
RP
RH
RPH.
The differences in power-on timing should not present a migration challenge for most applications where the
flash interfaces directly with a Host that requires oscillator and PLL lock prior to initiating the first boot read
access to the flash. In applications which may access the flash within 300 µs of power application, some
circuit modification will be required to accommodate migration to GL-S flash.
To initiate the first read or write cycle after power on, the GL-S requires CE# or OE# to transition from High to
Low no sooner than t
after V
exceeds V
and V
exceeds V
. CE# or OE# must be High at
VCS
CC
CC_min
IO
IO_min
least t
= 20 ns prior to CE# or OE# falling edge which initiates the first access.
CEH
CE# is ignored during Warm Reset; however, to initiate the first read or write cycle after warm reset, the GL-S
requires CE# to transition from High to Low no sooner than t
after RESET# transitions from Low to High.
RH
CE# must be high at least t
= 20 ns prior to CE# falling edge, which initiates first access. These were not
CEH
requirements for the GL-P so designs that have CE# fixed low cannot migrate to GL-S without modification to
enable active CE# control.
The GL-S allows V
to ramp concurrently with or after V
with no restriction on time or voltage differential.
IO
CC
During power ramp no input is allowed to exceed V
. The GL-S data sheet provides enhanced direction on
IO
power management and control to design a robust and reliable system.
®
October 22, 2012 S29GL-P_00_A14
S29GL-P MirrorBit
Flash Family
77