S29GL032N SPANSION [SPANSION], S29GL032N Datasheet - Page 17

• Manufacturer Part Number: S29GL032N
• Description: 64 Megabit, 32 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 110 nm MirrorBit Process Technology
• Manufacturer: SPANSION [SPANSION]

Legend
L = Logic Low = V
H = Logic High = V
V
V
X = Don’t Care
SA = Sector Address
A
D
D
Notes
1. If WP# = V
2. D
8.1
8.2
November 16, 2007 S29GL-N_01_09
Read
Write (Program/Erase)
Accelerated Program
Standby
Output Disable
Reset
ID
HH
IN
IN
OUT
= VIH, the first or last sector, or the two outer boot sectors are protected or unprotected as determined by the method described in Write Protect (WP#). All
sectors are unprotected when shipped from the factory (The Secured Silicon Sector may be factory protected depending on version ordered.)
= 11.5–12.5 V
= Address In
= Data In
= 11.5–12.5 V
IN
= Data Out
or D
Operation
OUT
Word/Byte Configuration
Requirements for Reading Array Data
IL
, the first or last sector remains protected (for uniform sector devices), and the two outer boot sectors are protected (for boot sector devices). If WP#
as required by command sequence, data polling, or sector protect algorithm (see
IL
IH
execute the command. The contents of the register serve as inputs to the internal state machine. The state
machine outputs dictate the function of the device.
control levels they require, and the resulting output. The following subsections describe each of these
operations in further detail.
The BYTE# pin controls whether the device data I/O pins operate in the byte or word configuration. If the
BYTE# pin is set at logic 1, the device is in word configuration, DQ0–DQ15 are active and controlled by CE#
and OE#.
If the BYTE# pin is set at logic 0, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used
as an input for the LSB (A-1) address function.
To read array data from the outputs, the system must drive the CE# and OE# pins to V
control and selects the device. OE# is the output control and gates array data to the output pins. WE# should
remain at V
The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses
on the device address inputs produce valid data on the device data outputs. The device remains enabled for
read access until the command register contents are altered.
See
timing specifications and the timing diagram. Refer to the DC Characteristics table for the active current
specification on reading array data.
Reading Array Data on page 41
V
IH
CC
.
CE#
± 0.3V
X
L
L
L
L
OE#
H
H
X
H
X
L
D a t a
Table 8.1 Device Bus Operations
WE#
S29GL-N MirrorBit
H
X
H
X
L
L
S h e e t
V
RESET#
CC
for more information. Refer to the AC Read-Only Operations table for
H
H
H
± 0.3V
H
L
®
(Note 1)
(Note 1)
Flash Family
WP#
X
X
X
X
Table 8.1
ACC
V
Figure 10.5 on page
X
X
H
X
X
HH
lists the device bus operations, the inputs and
Addresses
A
A
A
X
X
X
IN
IN
IN
56).
(Note 2)
(Note 2)
High-Z
High-Z
High-Z
DQ0–
D
DQ7
OUT
(Note 2)
(Note 2)
IL
BYTE#
High-Z
High-Z
High-Z
D
= V
. CE# is the power
OUT
IH
DQ8–DQ15
DQ15 = A-1
DQ8–DQ14
= High-Z,
BYTE#
High-Z
High-Z
High-Z
= V
IL
17