SC16C750B Philips Semiconductors, SC16C750B Datasheet - Page 10

• Manufacturer Part Number: SC16C750B
• Description: 5 V/ 3.3 V and 2.5 V UART with 64-byte FIFOs
• Manufacturer: Philips Semiconductors

Philips Semiconductors
9397 750 14453
Product data
6.2 FIFO operation
Table 3:
[1]
[2]
The 64-byte transmit and receive data FIFOs are enabled by the FIFO Control
Register bit-0 (FCR[0]). The receiver FIFO section includes a time-out function to
ensure data is delivered to the external CPU. An interrupt is generated whenever the
Receive Holding Register (RHR) has not been read following the loading of a
character or the receive trigger level has not been reached.
Table 4:
A2
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)
0
0
0
0
1
1
1
1
Baud rate register set (DLL/DLM)
0
0
Selected trigger level
(characters)
16-byte FIFO
1
4
8
14
64-byte FIFO
1
16
32
56
These registers are accessible only when LCR[7] is a logic 0.
These registers are accessible only when LCR[7] is a logic 1.
A1
0
0
1
1
0
0
1
1
0
0
Internal registers decoding
Flow control mechanism
A0
0
1
0
1
0
1
0
1
0
1
Rev. 03 — 13 December 2004
READ mode
Receive Holding Register
Interrupt Enable Register
Interrupt Status Register
Line Control Register
Modem Control Register
Line Status Register
Modem Status Register
Scratchpad Register
LSB of Divisor Latch
MSB of Divisor Latch
INT pin activation
1
4
8
14
1
16
32
56
[2]
5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs
Negate RTS
1
4
8
14
1
16
32
56
WRITE mode
Transmit Holding Register
Interrupt Enable Register
FIFO Control Register
Line Control Register
Modem Control Register
n/a
n/a
Scratchpad Register
LSB of Divisor Latch
MSB of Divisor Latch
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
SC16C750B
[1]
Assert RTS
0
0
0
0
0
0
0
0
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