SC16C750B Philips Semiconductors, SC16C750B Datasheet - Page 16

• Manufacturer Part Number: SC16C750B
• Description: 5 V/ 3.3 V and 2.5 V UART with 64-byte FIFOs
• Manufacturer: Philips Semiconductors

Philips Semiconductors
7. Register descriptions
Table 8:
[1]
[2]
[3]
9397 750 14453
Product data
A2 A1 A0 Register Default
General Register Set
0
0
0
0
0
0
1
1
1
1
Special Register Set
0
0
The value shown represents the register’s initialized HEX value; X = n/a.
These registers are accessible only when LCR[7] = 0.
The Special Register set is accessible only when LCR[7] is set to a logic 1.
0
0
0
1
1
1
0
0
1
1
0
0
0
0
1
0
0
1
0
1
0
1
0
1
SC16C750B internal registers
LCR
MCR
RHR
THR
IER
FCR
ISR
LSR
MSR
SPR
DLL
DLM
[3]
[2]
XX
XX
00
00
01
00
00
60
X0
FF
XX
XX
Table 8
The assigned bit functions are more fully defined in
[1]
Bit 7
bit 7
bit 7
0
RCVR
trigger
(MSB)
FIFOs
enabled
divisor
latch
enable
0
FIFO
data
error
DCD
bit 7
bit 7
bit 15
details the assigned bit functions for the fifteen SC16C750B internal registers.
Rev. 03 — 13 December 2004
Bit 6
bit 6
bit 6
0
RCVR
trigger
(LSB)
FIFOs
enabled
set break set parity even
0
trans.
empty
RI
bit 6
bit 6
bit 14
Bit 5
bit 5
bit 5
low
power
mode
64-byte
FIFO
enable
64-byte
FIFO
enable
flow
control
enable
trans.
holding
empty
DSR
bit 5
bit 5
bit 13
loop back OUT2,
Bit 4
bit 4
bit 4
Sleep
mode
reserved
0
parity
break
interrupt
CTS
bit 4
bit 4
bit 12
5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs
Bit 3
bit 3
bit 3
modem
status
interrupt
DMA
mode
select
INT
priority
bit 2
parity
enable
INT
enable
framing
error
bit 3
bit 3
bit 11
DCD
Section 7.1
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Bit 2
bit 2
bit 2
receive
line
status
interrupt
XMIT
FIFO
reset
INT
priority
bit 1
stop bits word
OUT1
parity
error
bit 2
bit 2
bit 10
RI
SC16C750B
through
Bit 1
bit 1
bit 1
transmit
holding
register
RCVR
FIFO
reset
INT
priority
bit 0
length
bit 1
RTS
overrun
error
bit 1
bit 1
bit 9
DSR
Section
Bit 0
bit 0
bit 0
receive
holding
register
FIFO
enable
INT
status
word
length
bit 0
DTR
receive
data
ready
bit 0
bit 0
bit 8
CTS
16 of 44
7.10.