SC16C750B Philips Semiconductors, SC16C750B Datasheet - Page 7

• Manufacturer Part Number: SC16C750B
• Description: 5 V/ 3.3 V and 2.5 V UART with 64-byte FIFOs
• Manufacturer: Philips Semiconductors

Philips Semiconductors
Table 2:
9397 750 14453
Product data
Symbol
OUT1,
OUT2
OUT
RCLK
RESET
IOR
IOR
RI
RTS
RXRDY
RX
Pin description
Pin
PLCC44 LQFP64
38, 35
-
10
39
25
24
43
36
32
11
30, 25
-
54
32
10
9
38
26
21
55
…continued
HVQFN32
-
23
4
24
-
14
-
21
19
5
Type
O
O
I
I
I
I
I
O
O
I
Rev. 03 — 13 December 2004
Description
Outputs 1 and 2. These are user-designated output terminals that
are set to the active (low) level by setting respective modem control
register (MCR) bits (OUT1 and OUT2). OUT1 and OUT2 are set to
inactive the (HIGH) level as a result of Master Reset, during loop
mode operations, or by clearing bit 2 (OUT1) or bit 3 (OUT2) of the
MCR.
Receiver clock. RCLK is the 16 baud rate clock for the receiver
section of the UART.
Master Reset. When active (HIGH), RESET clears most UART
registers and sets the levels of various output signals.
Read inputs. When either IOR or IOR is active (LOW or HIGH,
respectively) while the UART is selected, the CPU is allowed to
read status information or data from a selected UART register. Only
one of these inputs is required for the transfer of data during a read
operation; the other input should be tied to its inactive level (i.e.,
IOR tied LOW or IOR tied HIGH).
Ring indicator. RI is a modem status signal. Its condition can be
checked by reading bit 6 (RI) of the modem status register. Bit 2
( RI) of the modem status register indicates that RI has transitioned
from a LOW to a HIGH level since the last read from the modem
status register. If the modem status interrupt is enabled when this
transition occurs, an interrupt is generated.
Request to send. When active, RTS informs the modem or data
set that the UART is ready to receive data. RTS is set to the active
level by setting the RTS modem control register bit and is set to the
inactive (HIGH) level either as a result of a Master Reset or during
loop mode operations or by clearing bit 1 (RTS) of the MCR. In the
auto-RTS mode, RTS is set to the inactive level by the receiver
threshold control logic.
Receiver ready. Receiver direct memory access (DMA) signaling is
available with RXRDY. When operating in the FIFO mode, one of
two types of DMA signaling can be selected using the FIFO control
register bit 3 (FCR[3]). When operating in the 16C450 mode, only
DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in
which a transfer is made between CPU bus cycles. Mode 1
supports multi-transfer DMA in which multiple transfers are made
continuously until the receiver FIFO has been emptied. In DMA
mode 0 (FCR0 = 0 or FCR0 = 1, FCR3 = 0), when there is at least
one character in the receiver FIFO or receiver holding register,
RXRDY is active (LOW). When RXRDY has been active but there
are no characters in the FIFO or holding register, RXRDY goes
inactive (HIGH). In DMA mode 1 (FCR0 = 1, FCR3 = 1), when the
trigger level or the time-out has been reached, RXRDY goes active
(LOW); when it has been active but there are no more characters in
the FIFO or holding register, it goes inactive (HIGH).
Serial data input. RX is serial data input from a connected
communications device.
5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
SC16C750B
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