MT48LC16M4A2 Micron Technology, MT48LC16M4A2 Datasheet - Page 16

• Manufacturer Part Number: MT48LC16M4A2
• Description: SYNCHRONOUS DRAM
• Manufacturer: Micron Technology

before the clock edge at which the last desired data
element is valid, where x equals the CAS latency minus
one. This is shown in Figure 7 for CAS latencies of two
and three; data element n + 3 is either the last of a burst
of four or the last desired of a longer burst. The 64Mb
SDRAM uses a pipelined architecture and therefore
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
COMMAND
COMMAND
ADDRESS
ADDRESS
NOTE: Each READ command may be to any bank. DQM is LOW.
CLK
CLK
DQ
DQ
BANK,
T0
T0
COL n
BANK,
COL n
READ
READ
CAS Latency = 2
CAS Latency = 3
T1
T1
NOP
NOP
Consecutive READ Bursts
T2
T2
NOP
NOP
D
OUT
n
Figure 7
T3
T3
16
NOP
NOP
D
n + 1
D
OUT
does not require the 2n rule associated with a prefetch
architecture. A READ command can be initiated on any
clock cycle following a previous READ command. Full-
speed random read accesses can be performed to the
same bank, as shown in Figure 8, or each subsequent
READ may be performed to a different bank.
OUT
n
TRANSITIONING DATA
T4
T4
BANK,
BANK,
READ
COL b
READ
COL b
X = 1 cycle
n + 2
n + 1
D
D
Micron Technology, Inc., reserves the right to change products or specifications without notice.
OUT
OUT
X = 2 cycles
T5
T5
NOP
NOP
n + 2
n + 3
D
D
OUT
OUT
64Mb: x4, x8, x16
T6
T6
NOP
NOP
n + 3
D
D
OUT
OUT
b
DON’T CARE
T7
NOP
©2003, Micron Technology, Inc.
D
SDRAM
OUT
b