MT48LC16M4A2 Micron Technology, MT48LC16M4A2 Datasheet - Page 53

• Manufacturer Part Number: MT48LC16M4A2
• Description: SYNCHRONOUS DRAM
• Manufacturer: Micron Technology

TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTE: 1. x16: A8, A9 and A11 = “Don’t Care”
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
DQML, DQMH
SYMBOL*
t
t
t
t
t
t
t
AH
AS
CH
CL
CK(3)
CK(2)
CKH
COMMAND
A0-A9, A11
BA0, BA1
DQM /
CKE
A10
2.
3. Page left open; no
CLK
DQ
t
WR must be satisfied prior to PRECHARGE command.
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
x8: A9 and A11 = “Don’t Care”
x4: A11 = “Don’t Care”
1.5
2.5
2.5
1
6
–
1
t CMS
t CKS
t AS
t AS
t AS
-6
ACTIVE
BANK
T0
ROW
ROW
t CKH
t CMH
t AH
t AH
t AH
0.8
1.5
2.5
2.5
7.5
0.8
t RCD
7
-7E
t CL
t
RP.
T1
NOP
t CH
0.8
1.5
2.5
2.5
7.5
0.8
10
-75
t CMS
t CK
t DS
COLUMN m 1
D
T2
WRITE
BANK
WRITE – FULL-PAGE BURST
10
IN
1
2
3
3
8
1
t CMH
-8E
m
t DH
t DS
D
ns
ns
ns
ns
ns
ns
ns
IN
T3
NOP
m + 1
t DH
53
1,024 (x4) locations within same row
256 (x16) locations within same row
512 (x8) locations within same row
t DS
SYMBOL*
t
t
t
t
t
t
CKS
CMH
CMS
DH
DS
RCD
D
IN
T4
NOP
m + 2
t DH
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
Full page completed
1.5
1.5
1.5
18
1
1
t DS
-6
D
IN
T5
NOP
m + 3
t DH
(
(
(
(
(
1.5
0.8
1.5
0.8
1.5
(
)
(
)
(
)
(
)
(
)
15
(
)
)
)
)
)
(
)
(
(
)
(
(
)
(
(
(
(
(
)
)
)
)
)
)
)
)
(
(
(
(
(
(
)
)
)
)
)
(
(
(
)
(
)
(
)
)
)
)
-7E
64Mb: x4, x8, x16
t DS
Tn + 1
D
IN
NOP
m - 1
t DH
Full-page burst does
not self-terminate. Can
use BURST TERMINATE
command to stop.
1.5
0.8
1.5
0.8
1.5
20
-75
t DS
BURST TERM
Tn + 2
©2003, Micron Technology, Inc.
20
2
1
2
1
2
SDRAM
t DH
-8E
2, 3
DON’T CARE
Tn + 3
ns
ns
ns
ns
ns
ns
NOP