MT48LC16M4A2 Micron Technology, MT48LC16M4A2 Datasheet - Page 38

• Manufacturer Part Number: MT48LC16M4A2
• Description: SYNCHRONOUS DRAM
• Manufacturer: Micron Technology

TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 2, the CAS latency = 3, and auto precharge is disabled.
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
DQML, DQMH
SYMBOL*
t
t
t
t
t
t
t
t
t
AC(3)
AC(2)
AH
AS
CH
CL
CK(3)
CK(2)
CKH
COMMAND
A0-A9, A11
DQM /
BA0, BA1
CKE
A10
CLK
DQ
2. x16: A8, A9 and A11 = “Don’t Care”
t CMS
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
x8: A9 and A11 = “Don’t Care”
x4: A11 = “Don’t Care”
t CKS
1.5
2.5
2.5
t AS
t AS
t AS
COLUMN m
1
6
–
1
READ
T0
-6
BANK
t CMH
t CKH
t AH
t AH
t AH
5.5
–
2
t CMS
0.8
1.5
2.5
2.5
7.5
0.8
t CK
7
-7E
T1
NOP
t CMH
5.4
5.4
0.8
1.5
2.5
2.5
7.5
0.8
10
t CL
t CKS t CKH
-75
T2
NOP
5.4
t LZ
6
t CH
t AC
10
1
2
3
3
8
1
CLOCK SUSPEND MODE
-8E
T3
6
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
D
OUT
m
T4
NOP
38
t OH
t AC
SYMBOL*
t
t
t
t
t
t
t
t
t
CKS
CMH
CMS
DH
DS
HZ(3)
HZ(2)
LZ
OH
D
T5
OUT
NOP
m + 1
t HZ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
1.5
1.5
1.5
1
1
1
2
1
-6
T6
NOP
5.5
–
1.5
0.8
1.5
0.8
1.5
1
3
-7E
COLUMN e 2
t DS
64Mb: x4, x8, x16
BANK
WRITE
5.4
5.4
D
T7
IN
e
t DH
1.5
0.8
1.5
0.8
1.5
1
3
-75
5.4
6
T8
©2003, Micron Technology, Inc.
2
1
2
1
2
1
3
SDRAM
-8E
6
7
D
DON’T CARE
UNDEFINED
IN
T9
NOP
e + 1
ns
ns
ns
ns
ns
ns
ns
ns
ns