AD7476ART Analog Devices, AD7476ART Datasheet - Page 11

• Manufacturer Part Number: AD7476ART
• Description: 1 MSPS/ 12-/10-/8-Bit ADCs in 6-Lead SOT-23
• Manufacturer: Analog Devices

Digital Inputs
The digital inputs applied to the AD7476/AD7477/AD7478 are
not limited by the maximum ratings which limit the analog in-
puts. Instead, the digitals inputs applied can go to 7 V and are
–50
–55
–60
–65
–70
–75
–80
–85
–90
–72
–74
–76
–78
–80
–82
–84
10k
10k
INPUT FREQUENCY – Hz
INPUT FREQUENCY – Hz
SDATA
SDATA
SCLK
SCLK
100k
100k
CS
CS
V
DD
= 5.25V
V
V
DD
V
DD
DD
= 2.7V
V
V
V
= 2.35V
1
DD
DD
DD
1
V
= 3.6V
V
V
DD
DD
DD
= 3.6V
= 4.75V
= 5.25V
2
= 4.75V
= 2.35V
= 2.7V
4 LEADING ZEROS + CONVERSION RESULT
1M
1M
not restricted by the V
For example, if the AD7476/AD7477/AD7478 were operated with
a V
inputs. However, it is important to note that the data output
on SDATA will still have 3 V logic levels when V
Another advantage of SCLK and CS not being restricted by
the V
issues are avoided. If CS or SCLK are applied before V
there is no risk of latch-up as there would be on the analog inputs
if a signal greater than 0.3 V was applied prior to V
MODES OF OPERATION
The mode of operation of the AD7476/AD7477/AD7478 is
selected by controlling the (logic) state of the CS signal during a
conversion. There are two possible modes of operation, Normal
Mode and Power-Down Mode. The point at which CS is pulled
high after the conversion has been initiated will determine whether
or not the AD7476/AD7477/AD7478 will enter power-down
mode. Similarly, if already in power-down, CS can control whether
the device will return to normal operation or remain in power-
down. These modes of operation are designed to provide flexible
power management options. These options can be chosen to
optimize the power dissipation/throughput rate ratio for differ-
ing application requirements.
Normal Mode
This mode is intended for fastest throughput rate performance,
as the user does not have to worry about any power-up times
with the AD7476/AD7477/AD7478 remaining fully powered all
the time. Figure 17 shows the general diagram of the opera-
tion of the AD7476/AD7477/AD7478 in this mode.
The conversion is initiated on the falling edge of CS as described in
the Serial Interface section. To ensure the part remains fully
powered up at all times, CS must remain low until at least
10 SCLK falling edges have elapsed after the falling edge of CS.
If CS is brought high any time after the 10th SCLK falling edge,
but before the 16th SCLK falling edge, the part will remain
powered up but the conversion will be terminated and SDATA
will go back into three-state. Sixteen serial clock cycles are
DD
10
THREE-STATE
DD
10
of 3 V, then 5 V logic levels could be used on the digital
+ 0.3 V limit is the fact that power supply sequencing
AD7476/AD7477/AD7478
DD
16
16
+ 0.3 V limit as on the analog inputs.
DD
DD
.
DD
= 3 V.
then