AD7476ART Analog Devices, AD7476ART Datasheet - Page 13

• Manufacturer Part Number: AD7476ART
• Description: 1 MSPS/ 12-/10-/8-Bit ADCs in 6-Lead SOT-23
• Manufacturer: Analog Devices

POWER VERSUS THROUGHPUT RATE
By using the power-down mode on the AD7476/AD7477/AD7478
when not converting, the average power consumption of the
ADC decreases at lower throughput rates. Figure 20 shows how
as the throughput rate is reduced, the device remains in its power-
down state longer and the average power consumption over time
drops accordingly.
For example if the AD7476/AD7477/AD7478 is operated in a
continuous sampling mode with a throughput rate of 100 kSPS
and a SCLK of 20 MHz (V
in the power-down mode between conversions, then the power
consumption is calculated as follows. The power dissipation
during normal operation is 17.5 mW (V
up time is one dummy cycle, i.e., 1 µs, and the remaining
conversion time is another cycle, i.e., 1 µs, then the AD7476/
AD7477/AD7478 can be said to dissipate 17.5 mW for 2 µs
during each conversion cycle. If the throughput rate is 100 kSPS,
the cycle time is 10 µs and the average power dissipated during
each cycle is (2/10) × (17.5 mW) = 3.5 mW. If V
SCLK = 20 MHz and the device is again in power-down mode
between conversions, the power dissipation during normal opera-
tion is 4.8 mW. The AD7476/AD7477/AD7478 can now be said
to dissipate 4.8 mW for 2 µs during each conversion cycle. With
a throughput rate of 100 kSPS, the average power dissipated
during each cycle is (2/10) × (4.8 mW) = 0.96 mW. Figure
20 shows the power versus throughput rate when using the
power-down mode between conversions with both 5 V and
3 V supplies.
0.01
100
0.1
10
1
0
50
100
THROUGHPUT – kSPS
DD
150
V
= 5 V), and the device is placed
DD
= 5V, SCLK = 20MHz
V
200
DD
= 3V, SCLK = 20MHz
DD
250
= 5 V). If the power-
300
DD
= 3 V,
350
The power-down mode is intended for use with throughput
rates of approximately 333 kSPS and under as at higher sam-
pling rates power is not saved by using the power-down mode.
SERIAL INTERFACE
Figures 21, 22, and 23 show the detailed timing diagram for
serial interfacing to the AD7476, AD7477, and AD7478 respec-
tively. The serial clock provides the conversion clock and
also controls the transfer of information from the AD7476/
AD7477/AD7478 during conversion.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track and hold into hold mode,
takes the bus out of three-state and the analog input is sampled
at this point. The conversion is also initiated at this point and
will require 16 SCLK cycles to complete. Once 13 SCLK fall-
ing edges have elapsed, the track and hold will go back into
track on the next SCLK rising edge as shown in Figures 21, 22,
and 23 at Point B. On the 16th SCLK falling edge the SDATA
line will go back into three-state. If the rising edge of CS occurs
before 16 SCLKs have elapsed, the conversion will be terminated
and the SDATA line will go back into three-state; otherwise,
SDATA returns to three-state on the 16th SCLK falling edge as
shown in Figures 21, 22, and 23. Sixteen serial clock cycles
are required to perform the conversion process and to access
data from the AD7476/AD7477/AD7478. CS going low pro-
vides the first leading zero to be read in by the microcontroller
or DSP. The remaining data is then clocked out by subsequent
SCLK falling edges, beginning with the second leading zero. Thus
the first falling clock edge on the serial clock has the first lead-
ing zero provided and also clocks out the second leading zero.
The final bit in the data transfer is valid on the 16th falling
edge, having being clocked out on the previous (15th) falling
edge. In applications with a slower SCLK, it is possible to read
in data on each SCLK rising edge, i.e., the first rising edge of SCLK
after the CS falling edge would have the first leading zero pro-
vided and the 15th rising SCLK edge would have DB0 provided,
or the final zero provided for the AD7477 and AD7478.
AD7476/AD7477/AD7478